View WM898507_712919.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w
DESCRIPTION
The WM8985 is a low power, high quality, feature-rich stereo codec designed for portable multimedia applications that require low power consumption and high quality audio. The device integrates preamps for stereo differential mics, and includes class D and class AB drivers for headphone and differential or stereo line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced DSP features include a 5-band equaliser, an ALC/limiter for the microphone or line input through the ADC and a digital playback limiter. Additional digital filtering options are available in the ADC path, to cater for application filtering such as `wind noise reduction' and a programmable notch filter. Highly flexible mixers enable many new application features, with the option to record and playback any combination of voice, line inputs and digital audio such as FM Radio or MP3. The WM8985 digital audio interface can operate in master or slave mode, while an integrated PLL provides flexible clocking schemes. The WM8985 operates at analogue supply voltages from 2.5V to 3.3V, although the digital core can operate at voltages down to 1.71V to save power. Additional power management control enables individual sections of the chip to be powered down under software control.
WM8985
Multimedia CODEC With Class D Headphone and Line Out
FEATURES
Stereo Codec: * DAC SNR 98dB, THD -84dB (`A' weighted @ 48kHz) * ADC SNR 92.5dB, THD -83dB (`A' weighted @ 48kHz) * Headphone driver with `capless' option * 40mW/channel output power into 16 / 3.3V AVDD2 * Class D headphone driver * Class AB headphone / line Driver * PSRR 70dB at 217Hz * Stereo, mono or differential line output Mic Preamps: * Stereo differential or mono microphone interfaces * Programmable preamp gain * Pseudo differential inputs with common mode rejection * Programmable ALC / Noise Gate in ADC path * Low-noise bias supplied for electret microphones Other Features: * Enhanced 3-D function for improved stereo separation * Digital playback limiter * 5-band Equaliser (record or playback) * Programmable ADC High Pass Filter (wind noise reduction) * Programmable ADC Notch Filter * Aux inputs for stereo analog input signals or `beep' * PLL supporting various clocks between 8MHz-50MHz * Sample rates supported (kHz): 8, 11.025, 16, 12, 16, 22.05, 24, 32, 44.1, 48 * Low power, low voltage * 2.5V to 3.6V analogue supplies * 1.71V to 3.6V digital supplies * 5x5mm 32-lead QFN package
APPLICATIONS
* * Portable audio player / FM radio Multimedia Mobile Handsets
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Pre-Production, March 2007, Rev 3.5
Copyright (c)2007 Wolfson Microelectronics plc
WM8985 BLOCK DIAGRAM
Pre-Production
w
PP, Rev 3.5, March 2007 2
Pre-Production
WM8985 TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 PIN CONFIGURATION...........................................................................................5 ORDERING INFORMATION ..................................................................................5 PIN DESCRIPTION ................................................................................................6 ABSOLUTE MAXIMUM RATINGS.........................................................................7 RECOMMENDED OPERATING CONDITIONS .....................................................7 ELECTRICAL CHARACTERISTICS ......................................................................8
TERMINOLOGY .......................................................................................................... 14
AUDIO PATHS OVERVIEW .................................................................................16 SIGNAL TIMING REQUIREMENTS .....................................................................17
SYSTEM CLOCK TIMING ........................................................................................... 17 AUDIO INTERFACE TIMING - MASTER MODE ........................................................ 17 AUDIO INTERFACE TIMING - SLAVE MODE............................................................ 18 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 19 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 20
INTERNAL POWER ON RESET CIRCUIT ..........................................................21
RECOMMENDED POWER UP/DOWN SEQUENCE .................................................. 23
DEVICE DESCRIPTION.......................................................................................27
INTRODUCTION ......................................................................................................... 27 INPUT SIGNAL PATH ................................................................................................. 28 ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 38 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 42 LIMITER MODE........................................................................................................... 45 OUTPUT SIGNAL PATH ............................................................................................. 54 3D STEREO ENHANCEMENT .................................................................................... 61 ANALOGUE OUTPUTS............................................................................................... 61 DIGITAL AUDIO INTERFACES................................................................................... 74 AUDIO SAMPLE RATES ............................................................................................. 78 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 79 COMPANDING............................................................................................................ 81 GENERAL PURPOSE INPUT/OUTPUT...................................................................... 83 OUTPUT SWITCHING (JACK DETECT)..................................................................... 84 CONTROL INTERFACE.............................................................................................. 85 RESETTING THE CHIP .............................................................................................. 86 POWER SUPPLIES .................................................................................................... 86 POWER MANAGEMENT ............................................................................................ 87
REGISTER MAP...................................................................................................89
REGISTER BITS BY ADDRESS ................................................................................. 91
DIGITAL FILTER CHARACTERISTICS .............................................................109
TERMINOLOGY ........................................................................................................ 109 DAC FILTER RESPONSES....................................................................................... 110 ADC FILTER RESPONSES....................................................................................... 110 HIGHPASS FILTER................................................................................................... 111 5-BAND EQUALISER ................................................................................................ 112
w
PP, Rev 3.5, January 2007 3
WM8985
Pre-Production
APPLICATIONS INFORMATION .......................................................................116
RECOMMENDED EXTERNAL COMPONENTS ........................................................ 116
PACKAGE DIAGRAM ........................................................................................117
ADDRESS: ................................................................................................................ 118
w
PP, Rev 3.5, March 2007 4
Pre-Production
WM8985
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE WM8985GEFL WM8985GEFL/R Note: Reel quantity = 3,500 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 32-lead QFN (5 x 5 mm) (Pb-free) 32-lead QFN (5 x 5 mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260oC 260oC
w
PP, Rev 3.5, January 2007 5
WM8985 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME LIP LIN L2/GPIO2 RIP RIN R2/GPIO3 LRC BCLK ADCDAT DACDAT MCLK DGND DCVDD DBVDD CSB/GPIO1 SCLK SDIN MODE AUXL AUXR OUT4 OUT3 ROUT2 AGND2 LOUT2 AVDD2 VMID AGND1 ROUT1 LOUT1 AVDD1 MICBIAS TYPE Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Digital Input / Output Digital Input / Output Digital Output Digital Input Digital Input Supply Supply Supply Digital Input / Output Digital Input Digital Input / Output Digital Input Analogue input Analogue input Analogue Output Analogue Output Analogue Output Supply Analogue Output Supply Reference Supply Analogue Output Analogue Output Supply Analogue Output DESCRIPTION Left MIC pre-amp positive input Left MIC pre-amp negative input
Pre-Production
Left channel line input/secondary mic pre-amp positive input/GPIO2 pin Right MIC pre-amp positive input Right MIC pre-amp negative input Right channel line input/secondary mic pre-amp positive input/GPIO3 pin DAC and ADC sample rate clock Digital audio bit clock ADC digital audio data output DAC digital audio data input Master clock input Digital ground Digital core logic supply Digital buffer (I/O) supply 3-Wire control interface chip Select / GPIO1 pin 3-Wire control interface clock input / 2-wire control interface clock input 3-Wire control interface data input / 2-Wire control interface data input Control interface selection Left auxiliary input Right auxiliary input Right line output / mono mix output Left line output Class D or class AB headphone output right Analogue ground (ground reference for ROUT2/LOUT2 and OUT3/OUT4) Class D or class AB headphone output left Analogue supply (feeds output amplifiers ROUT2/LOUT2 and OUT3/OUT4) Decoupling for ADC and DAC reference voltage Analogue ground (ground reference for all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, ROUT1) Class AB headphone or line output right Class AB headphone or line output left Analogue supply (feeds all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, LOUT2)) Microphone bias
Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. Refer to the application note WAN_0118 on "Guidelines on How to Use QFN Packages and Create Associated PCB Footprints"
w
PP, Rev 3.5, March 2007 6
Pre-Production
WM8985
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION DBVDD, DCVDD, AVDD1, AVDD2 supply voltages Voltage range digital inputs Voltage range analogue inputs Storage temperature prior to soldering Storage temperature after soldering Notes: 1. 2. 3. 4. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are internally independent (i.e. not connected). Analogue supply voltages should not be less than digital supply voltages. DBVDD must be greater than or equal to DCVDD. MIN -0.3V DGND -0.3V AGND1 -0.3V -65C MAX +4.5V DBVDD +0.3V AVDD1 +0.3V +150C
30C max / 85% RH max
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supply range Ground Notes: 1. Analogue supply voltages should not be less than digital supply voltages. SYMBOL DCVDD DBVDD AVDD1, AVDD2 DGND, AGND1, AGND2 TEST CONDITIONS MIN 1.711 1.71 2.51 0 TYP MAX 3.6 3.6 3.6 UNIT V V V V
w
PP, Rev 3.5, January 2007 7
WM8985 ELECTRICAL CHARACTERISTICS
Pre-Production
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Input PGA Inputs (LIP, LIN, RIP, RIN, L2, R2) INPPGAVOLL, INPPGAVOLR, PGABOOSTL and PGABOOSTR = 0dB Full-scale Input Signal Level - Single-ended input via LIN/RIN 1 Full-scale Input Signal Level - Pseudo-differential input 1,2 Input PGA equivalent input noise INPPGAVOLL/R = +35.25dB No input signal 0 to 20kHz INPPGAVOLL and INPPGAVOLR = +35.25dB INPPGAVOLL and INPPGAVOLR = 0dB INPPGAVOLL and INPPGAVOLR = -12dB All gain settings L2_2INPPGA and R2_2INPPGA = 1 L2_2BOOSTVOL and R2_2BOOSTVOL = 000 L2_2INPPGA and R2_2INPPGA = 0 L2_2BOOSTVOL and R2_2BOOSTVOL = +6dB L2_2INPPGA and R2_2INPPGA = 0 L2_2BOOSTVOL and R2_2BOOSTVOL = 0dB L2_2INPPGA and R2_2INPPGA = 0 L2_2BOOSTVOL and R2_2BOOSTVOL = -12dB All analogue input pins Gain adjusted by INPPGAVOLL and INPPGAVOLL Guaranteed monotonic INPPGAMUTEL and INPPGAMUTER = 1 PGABOOSTL and PGABOOSTR = 0 PGABOOSTL and PGABOOSTR = 1 -12 AVDD/3.3 AVDD*0.7/ 3.3 150 Vrms Vrms
V
LIN, RIN input resistance LIN, RIN input resistance LIN, RIN input resistance LIP, RIP input resistance L2, R2 input resistance
1.6 46 71 90 90
k k k k k
L2, R2 input resistance
11
k
L2, R2 input resistance
22
k
L2, R2 input resistance
60
k
Input Capacitance Input PGA Programmable Gain
10 +35.25
pF dB
Programmable Gain Step Size Input PGA Mute Attenuation Input Gain Boost Input Gain Boost
0.75 100 0 +20
dB dB dB dB
w
PP, Rev 3.5, March 2007 8
Pre-Production
WM8985
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full-scale Input Signal Level Input Resistance
2
SYMBOL
TEST CONDITIONS
MIN
TYP AVDD/3.3
MAX
UNIT Vrms k k k k k k pF
Auxiliary Analogue Inputs (AUXL, AUXR) Left Input boost and mixer enabled, at +6dB Left Input boost and mixer enabled, at 0dB gain Left Input boost and mixer enabled, at -12dB gain Right Input boost, mixer enabled, at +6dB gain Right Input boost, mixer enabled, at 0dB gain Right Input boost, mixer enabled, at -12dB gain Input Capacitance Gain range from AUXL and AUXR input to left and right input PGA mixers AUXLBOOSTVOL and AUXRBOOSTVOL step size L2, R2 Line Input Programmable Gain Gain range from L2/R2 input to left and right input PGA mixers L2/R2_2BOOSTVOL step size L2/R2_2BOOSTVOL mute attenuation OUT4 to left or right input boost record path Gain range into left and right input PGA mixers OUT4_2ADCVOL gain step size OUT4_2ADCVOL mute attenuation Gain adjusted by OUT4_2ADCVOL -6 3 100 +12 dB dB dB Gain adjusted by L2_2BOOSTVOL and R2_2BOOSTVOL -12 +6 dB All analogue Inputs Gain adjusted by AUXL2BOOSTVOL and AUXR2BOOSTVOL -12 11 22 60 11 22 60 10 +6
dB
3
dB
3 100
dB dB
Analogue to Digital Converter (ADC) - Input from LIN/P and RIN/P in differential configuration to input PGA INPPGAVOLL, INPPGAVOLR, PGABOOSTL, PGABOOSTR, ADCLVOL and ADCRVOL = 0dB Signal to Noise Ratio 3 SNR A-weighted AVDD1=AVDD2=3.3V A-weighted AVDD1=AVDD2=2.5V 22Hz to 20kHz AVDD1=AVDD2=3.3V 22Hz to 20kHz AVDD1=AVDD2=2.5V Total Harmonic Distortion 4 THD -7dBV Input AVDD1=AVDD2=3.3V -7dBV Input AVDD1=AVDD2=2.5V Total Harmonic Distortion + Noise 5 THD+N -7dBV Input AVDD1=AVDD2=3.3V -7dBV Input AVDD1=AVDD2=2.5V Channel Separation 6 1kHz full scale input signal 92.5 91.5 90 90 -75 -75 -72 -72 100 -68 -70 dB dB dB dB dB dB dB dB dB
Analogue to Digital Converter (ADC) - Input from L2, R2 into left and right PGA mixer. INPPGAVOLL, INPPGAVOLR,
w
PP, Rev 3.5, January 2007 9
WM8985
Pre-Production
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS L2_2BOOSTVOL, R2_2BOOSTVOL, ADCLVOL and ADCRVOL = 0dB Signal to Noise Ratio 3 SNR A-weighted AVDD1=AVDD2=3.3V A-weighted AVDD1=AVDD2=2.5V 22Hz to 20kHz AVDD1=AVDD2=3.3V 22Hz to 20kHz AVDD1=AVDD2=2.5V Total Harmonic Distortion 4 THD -1dBV Input AVDD1=AVDD2=3.3V -1dBV Input AVDD1=AVDD2=2.5V Total Harmonic Distortion + Noise 5 THD+N -1dBV Input AVDD1=AVDD2=3.3V -1dBV Input AVDD1=AVDD2=2.5V Channel Separation 6 1kHz input signal DAC to left and right mixers into 10k / 50pF load on LOUT1 and ROUT1 LOUT1VOL, ROUT1VOL, DACLVOL and DACRVOL = 0dB Full-scale output 1 Signal to Noise Ratio
3
MIN 85
TYP 92.5 92.5 90 90 -83 -66 -81 -65 100
MAX
UNIT dB dB dB dB
-78
dB dB
-70
dB dB dB
LOUT1VOL and ROUTVOL = 0dB SNR A-weighted AVDD1=AVDD2=3.3V A-weighted AVDD1=AVDD2=2.5V 22Hz to 20kHz AVDD1=AVDD2=3.3V 22Hz to 20kHz AVDD1=AVDD2=2.5V
AVDD1/3.3 98 96 95.5 93.5 -84 -84 -82 -82 100
Vrms dB dB dB dB dBFS dBFS dBFS dBFS dB
Total Harmonic Distortion 4
THD
0dBFS input AVDD1=AVDD2=3.3V 0dBFS input AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
5
THD+N
0dBFS input AVDD1=AVDD2=3.3V 0dBFS input AVDD1=AVDD2=2.5V
Channel Separation
6
1kHz signal
w
PP, Rev 3.5, March 2007 10
Pre-Production
WM8985
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to L/R mixer into 10k / 50pF load on L/ROUT2, class AB mode LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0dB Full-scale output 1 Signal to Noise Ratio
3
LOUT2VOL and ROUT2VOL = 0dB SNR A-weighted AVDD1=AVDD2=3.3V A-weighted AVDD1=AVDD2=2.5V 22Hz to 20kHz AVDD1=AVDD2=3.3V 22Hz to 20kHz AVDD1=AVDD2=2.5V
AVDD1/3.3 100 96 95.5 93.5 -84 -82 -82 -80 100 AVDD2/3.3
Vrms dB dB dB dB dBFS dBFS dBFS dBFS dB Vrms 92 -80 -78 dB dBFS dBFS dB
Total Harmonic Distortion 4
THD
0dBFS input AVDD1=AVDD2=3.3V 0dBFS input AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise 5
THD+N
0dBFS input AVDD1=AVDD2=3.3V 0dBFS input AVDD1=AVDD2=2.5V
Channel Separation 6 Full-scale output voltage Signal to Noise Ratio
3
1kHz input signal
DAC to OUT3 and OUT4 mixers into OUT3/OUT4 outputs into (10k / 50pF load. DACVOLL and DACVOLR = 0dB) SNR THD THD+N A-weighted AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=3.3V 1kHz signal 98 -84 -82 100
Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 Channel Separation 6
DAC to left and right mixer into headphone 16 load on LOUT1 and ROUT1 LOUT1VOL, ROUT1VOL, DACLVOL and DACRVOL = 0dB Full-scale output Signal to Noise Ratio
3
AVDD1/3.3 SNR A-weighted AVDD1=AVDD2=3.3V 22Hz to 20kHz AVDD1=AVDD2=3.3V 100 95.5 -79 -75 100
Vrms dB dB dB dB dB
Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 Channel Separation 6
THD THD+N
Po = 20mW, RL=16 Po = 20mW, RL=16 1kHz signal
w
PP, Rev 3.5, January 2007 11
WM8985
Pre-Production
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to left and right mixer into headphone 16 load on LOUT2 and ROUT2, Class AB mode LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0dB Full-scale output Signal to Noise Ratio 3 SNR A-weighted AVDD1=AVDD2=3.3V 22Hz to 20kHz AVDD1=AVDD2=3.3V Total Harmonic Distortion 4 Total Harmonic Distortion + Noise 5 Channel Separation
6
AVDD1/3.3 97 95.5 -79 -75 100 -70
Vrms dB dB dB dB dB
THD THD+N
Po = 20mW, RL=16 Po = 20mW, RL=16 1kHz signal
DAC to left and right mixer into headphone 16 load on LOUT2 and ROUT2, Class D mode, Lfilter = 33nH Cfilter = 220nf LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0Db Full-scale output Signal to Noise Ratio 3 Total Harmonic Distortion 4 Channel Separation 6 PWM Rise Time PWM Fall Time PWM Switching Frequency Efficiency Power Supply Rejection Idle Current PSRR DCLKDIV = 1000 RL = 16, tPW = 20ns, PO = 20mW 100mVpp ripple @217Hz injected on AVDD2 No analogue output signal on either channel Gain adjusted by BYPLMIXVOL and BYPRMIXVOL -15 SNR THD A-weighted AVDD1=AVDD2=3.3V Po = 20mW, RL=16 1kHz signal 80 AVDD1/3.3 90 -79 100 1.5 1.5 1.4 72 70 0.5 Vrms dB dB dB ns ns MHz % dB mA
Bypass paths to left and right output mixers. BYPL2LMIX = 1 and BYPR2RMIX = 1 PGA gain range into mixer 0 +6 dB
BYPLMIXVOL and BYPRMIXVOL gain step into mixer Mute attenuation Analogue outputs (LOUT1, ROUT1, LOUT2, ROUT2) Programmable Gain range Gain adjusted by L/ROUT1VOL and L/ROUT2VOL Monotonic 1kHz, full scale signal L/ROUT1MUTE = 1 L/ROUT2MUTE = 1 -57 BYPL2LMIX = 0 BYPR2RMIX = 0
3 100
dB dB
0
+6
dB
Programmable Gain step size Mute attenuation
1 85
dB dB
w
PP, Rev 3.5, March 2007 12
Pre-Production
WM8985
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT LIN and RIN input PGA to input boost stage into 10k / 50pF load on OUT3/OUT4 outputs INPPGAVOLL, INPPGAVOLR, PGABOOSTL and PGABOOSTR = 0dB Full-scale output voltage, 0dB gain Signal to Noise Ratio
3
AVDD2/3.3 SNR A-weighted AVDD1=AVDD2=3.3V A-weighted AVDD1=AVDD2=2.5V 22Hz to 22kHz AVDD1=AVDD2=3.3V 22Hz to 22kHz AVDD1=AVDD2=2.5V 90 98 96 95.5 93.5 -84 -82 -82 -80 100
Vrms dB dB dB dB dBFS dBFS dBFS dBFS dB
Total Harmonic Distortion 4
THD
full-scale signal AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=2.5V
Total Harmonic Distortion + Noise
5
THD+N
full-scale signal AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=2.5V
Channel Separation 6 LIN and RIN into input PGA Bypass to LOUT1 and ROUT1 into 10k / 50pF loads BYPLMIXVOL, BYPRMIXVOL, LOUT1VOL and ROUT1VOL = 0dB Full-scale output voltage, 0dB gain Signal to Noise Ratio 3 SNR A-weighted AVDD1=AVDD2=3.3V A-weighted AVDD1=AVDD2=2.5V 22Hz to 22kHz AVDD1=AVDD2=3.3V 22Hz to 22kHz AVDD1=AVDD2=2.5V Total Harmonic Distortion 4 THD full-scale signal AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=2.5V Total Harmonic Distortion + Noise 5 THD+N full-scale signal AVDD1=AVDD2=3.3V full-scale signal AVDD1=AVDD2=2.5V Channel separation 6 Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage MBVSEL=0 MBVSEL=1 for VMICBIAS within +/-3% 1kHz to 20kHz 1kHz full scale signal 90
AVDD1/3.3 100 96 95.5 93.5 -87 -69 -85 -68 100 0.9*AVDD1 0.65*AVDD1 3 15 -73 -75
Vrms dB dB dB dB dBFS dBFS dBFS dBFS dB V V mA nV/Hz
w
PP, Rev 3.5, January 2007 13
WM8985
Pre-Production
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level Input Capacitance Input leakage VIH VIL VOH VOL IOL=1mA IOH-1mA All digital pins 10 TBD 0.9xDBV DD 0.1xDBVDD 0.7xDBV DD 0.3xDBVDD V V V V pF pA SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. Full-scale input and output levels scale in relation to AVDD or AVDD2 depending upon the input or output used. For example, when AVDD = 3.3V, 0dBFS = 1Vrms (0dBV). When AVDD < 3.3V the absolute level of 0dBFS will decrease with a linear relationship to AVDD. Input level to RIP and LIP in differential configurations is limited to a maximum of -3dB or performance will be reduced. Signal-to-noise ratio (dBFS) - SNR is the difference in level between a reference full scale output signal and the device output with no signal applied. This ratio is also called idle channel noise. (No Auto-zero or Automute function is employed in achieving these results). Total Harmonic Distortion (dB) - THD is the difference in level between a reference output signal and the first seven harmonics of the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the next seven harmonics is calculated. Total Harmonic Distortion plus Noise (dB) - THD+N is the difference in level between a reference output signal and the sum of the harmonics, wide-band noise and interference on the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the total harmonics, wide-band noise and interference is calculated. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
2. 3.
4.
5.
6.
w
PP, Rev 3.5, March 2007 14
Pre-Production
WM8985
POWER CONSUMPTION
Typical power consumption for various scenarios is shown below. All measurements are made with quiescent signal.
DCVDD(mA)
DBVDD(mA)
AVDD1(mA)
AVDD2(mA)
Description Off (Default Settings)
1.8 0.0002 1.8 0.0002 1.8 0.0002 3.3 0.006 3.6 0.008 1.8 1.8 1.8 3.3 3.6 1.8 1.8 3.3 3.6 1.8 1.8 3.3 3.6 0.002 0.002 0.002 0.006 0.008 3.336 3.336 7.182 8.098 3.57 3.57 7.603 8.529
1.8 3.3 3.3 3.3 3.6 1.8 3.3 3.3 3.3 3.6
0 0 0 0 0 0 0 0 0 0
2.5 3 3.3 3.3 3.6 2.5 3 3.3 3.3 3.6 2.5 3 3.3 3.6 2.5 2.7 3 3.3
0.01 0.011 0.012 0.011 0.012 0.117 0.138 0.149 0.149 0.157 2.238 2.728 3.025 3.325 4.76 4.967 5.272 5.578
2.5 3 3.3 3.3 3.6 2.5 3 3.3 3.3 3.6 2.5 3 3.3 3.6 2.5 3 3.3 3.6
0 0 0 0 0 0 0 0 0 0 0.28 0.35 0.39 0.44 0 0 0 0
0.03 0.03 0.04 0.06 0.07 0.30 0.42 0.50 0.51 0.59 12.31 15.24 34.98 42.80 18.35 19.88 40.99 49.21
Standby mode (Lowest Power)
DAC Playback 32 load L/ROUT2 - Class AB Mode fs=44.1kHz
1.8 0.003 3.3 0.0021 3.3 0.0021 3.6 0.025 1.8 3.3 3.3 3.6 0.013 0.013 0.026 0.027
ADC Stereo Line Record fs=44.1kHz
Table 1 Power Consumption Contact Wolfson for more information on device power consumption.
w
PP, Rev 3.5, January 2007 15
Total (mW)
DCVDD(V)
DBVDD(V)
AVDD1(V)
AVDD2(V)
WM8985 AUDIO PATHS OVERVIEW
Pre-Production
Figure 1 Audio Paths Overview
w
PP, Rev 3.5, March 2007 16
Pre-Production
WM8985
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA = +25oC, Slave Mode PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note: 1. PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz. TMCLKY TMCLKDS MCLK=SYSCLK (=256fs) MCLK input to PLL Note 1 81.38 20 60:40 40:60 ns ns SYMBOL CONDITIONS MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
Figure 3 Digital Audio Data Timing - Master Mode (see Control Interface)
w
PP, Rev 3.5, January 2007 17
WM8985
Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDDA tDST tDHT 10 10 10 10 SYMBOL TA=+25oC, MIN Master TYP
Pre-Production
Mode, MAX
fs=48kHz, UNIT ns ns ns ns
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 4 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low LRC set-up time to BCLK rising edge LRC hold time from BCLK rising edge DACDAT hold time from BCLK rising edge DACDAT set-up time to BCLK rising edge ADCDAT propagation delay from BCLK falling edge Note: BCLK period should always be greater than or equal to MCLK period. tBCY tBCH tBCL tLRSU tLRH tDH tDs tDD 50 20 20 10 10 10 10 10 ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
w
PP, Rev 3.5, March 2007 18
Pre-Production
WM8985
3-wire mode is selected by connecting the MODE pin high.
CONTROL INTERFACE TIMING - 3-WIRE MODE
Figure 5 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD1 = AVDD2 = 3.3V, DGND = AGND1 = AGND2 = 0V, TA=+25 C, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
o
w
PP, Rev 3.5, January 2007 19
WM8985
CONTROL INTERFACE TIMING - 2-WIRE MODE
2-wire mode is selected by connecting the MODE pin low.
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t5 t3
Pre-Production
t8
Figure 6 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL TA=+25oC, MIN Slave TYP Mode, MAX fs=48kHz, UNIT
w
PP, Rev 3.5, March 2007 20
Pre-Production
WM8985
INTERNAL POWER ON RESET CIRCUIT
Figure 7 Internal Power on Reset Circuit Schematic The WM8985 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1 and monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold.
Figure 8 Typical Power up Sequence where AVDD1 is Powered before DCVDD
Figure 8 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD1 is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the minimum threshold Vpora_off.
w
PP, Rev 3.5, January 2007 21
WM8985
Pre-Production
Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1
Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD1 rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpord_off.
SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off
MIN 0.4 0.9 0.4 0.5 0.4
TYP 0.6 1.2 0.6 0.7 0.6
MAX 0.8 1.6 0.8 0.9 0.8
UNIT V V V V V
Table 2 Typical POR Operation (Typical Simulated Values) Notes: 1. If AVDD1 and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. The chip will enter reset at power down when AVDD1 or DCVDD falls below Vpora_off or Vpord_off. This may be important if the supply is turned on and off frequently by a power management system. The minimum tpor period is maintained even if DCVDD and AVDD1 have zero rise time. This specification is guaranteed by design rather than test.
2.
3.
w
PP, Rev 3.5, March 2007 22
Pre-Production
WM8985
In order to minimise output pop and click noise, it is recommended that the WM8985 device is powered up and down under control using the following sequences: Power Up: 1. 2. 3. 4. 5. 6. 7. 8. 9. Turn on external power supplies. Wait for supply voltage to settle. Set low analogue bias mode, BIASCUT = 1 Enable thermal shutdown TSDEN = TSOPCTRL = 1 Enable Internal bias BIASEN = 1. Mute all outputs and set PGAs to minimum gain, R52 to R57 = 0x140h. Enable VMID independent current bias, POBCTRL = 1. Enable required outputs, DACs and mixers. Enable VMID with required charge time e.g. VMIDSEL=01. Wait 10ms (based on register updates of 325s)
RECOMMENDED POWER UP/DOWN SEQUENCE
10. Setup digital interface, input amplifiers, PLL, ADCs and DACs for desired operation. 11. Disable VMID independent current bias, POBCTRL = 0. 12. Wait 500ms 1 13. Unmute L/ROUT1 and set desired volume, e.g. for 0dB R52 and R53 = 0x139h. 14. Unmute L/ROUT2 and set desired volume, e.g. for 0dB R54 and R55 = 0x139h.
Power Down 2: 1. 2. 3. 4. 5. Disable Thermal shutdown, TSDEN = TSOPCTRL = 0 Disable VMIDSEL=00 and BIASEN=0 Wait for VMID to discharge 3 Power off registers R1, R2, R3 = 0x000h Remove external power supplies
Notes: 1. 2. 3. Charging time constant is determined by impedance selected by VMIDSEL and the value of decoupling capacitor connected to VMID pin. It is possible to interrupt the power down sequence and power up to VMID before the allocated VMID discharge time. This is done by following the power-up sequence omitting steps 4 to 8. Discharge time constant is determined by the values of analogue output capacitors.
w
PP, Rev 3.5, January 2007 23
WM8985
Pre-Production
Figure 10 ADC Power Up and Down Sequence (not to scale)
SYMBOL tmidrail_on tmidrail_off tadcint ADC Group Delay
MIN
TYPICAL 300 >6 2/fs 29/fs
MAX
UNIT ms s n/fs n/fs
Table 3 Typical POR Operation (Typical Simulated Values)
w
PP, Rev 3.5, March 2007 24
Pre-Production Notes: 1.
WM8985
The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD1 power supply rise time. The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling capacitor discharge time. The time, tmidrail_off, is measured using a 1F capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise but no significant digital output will be present. The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for normal ADC operation. ADCDAT data output delay from power up - with power supplies starting from 0V - is determined primarily by the VMID charge time. ADC initialisation and power management bits may be set immediately after POR is released; VMID charge time will be significantly longer and will dictate when the device is stabilised for analogue input. ADCDAT data output delay at power up from device standby (power supplies already applied) is determined by ADC initialisation time, 2/fs.
2.
3. 4. 5.
6.
Figure 11 DAC Power Up and Down Sequence (not to scale)
w
PP, Rev 3.5, January 2007 25
WM8985
SYMBOL tline_midrail_on tline_midrail_off thp_midrail_on thp__midrail_off tdacint DAC Group Delay MIN TYPICAL 300 >6 300 >6 2/fs 29/fs MAX UNIT ms s ms s n/fs n/fs
Pre-Production
Table 4 Typical POR Operation (Typical Simulated Values) Notes: 1. The lineout charge time, tline_midrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD1 power supply rise time. The values above were measured using a 4.7F capacitor. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute function has been applied to the signal beforehand. The lineout discharge time, tline_midrail_off, is determined by the VMID pin discharge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance. The values above were measured using a 4.7F capacitor. The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD1 power supply rise time. The values above were measured using a 4.7F VMID decoupling capacitor. The headphone discharge time, thp_midrail_off, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance. The values above were measured using a 4.7F VMID decoupling capacitor. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for normal DAC operation.
2.
3.
4.
5.
6.
w
PP, Rev 3.5, March 2007 26
Pre-Production
WM8985
DEVICE DESCRIPTION
INTRODUCTION
The WM8985 is a low power audio codec combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
MICROPHONE INPUTS
Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be pseudo-differentially connected, with user defined gain. The provision of the common mode input pin for each stereo input allows for rejection of common mode noise on the microphone inputs (level depends on gain setting chosen). A microphone bias is output from the chip which can be used to bias both microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant.
AUXILIARY ANALOG LINE INPUTS (AUXL, AUXR)
The inputs, AUXL and AUXR, can be used as a stereo line input or as an input for warning tones (or `beeps') etc. These inputs can be summed into the record paths, along with the microphone preamp outputs, so allowing for mixing of audio with `backing music' etc as required. Additional stereo analog signals might be connected to the Line inputs of WM8985 (e.g. melody chip or FM radio), and the stereo signal listened to via headphones, or recorded, simultaneously if required.
ADC
The stereo ADC uses a 24-bit high-order over sampling architecture to deliver optimum performance with low power consumption.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type applications, including MP3 players and portable disc players of all types.
OUTPUT MIXERS
Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to allow for all possible signal combinations.
w
PP, Rev 3.5, January 2007 27
WM8985
Pre-Production OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from the output of the DACs, the mixers or the input microphone boost stages. They can also provide a midrail reference for pseudo differential inputs to external amplifiers.
AUDIO INTERFACES
The WM8985 has a standard audio interface, to support the transmission of stereo data to and from the chip. This interface is a 3 wire standard audio interface which supports a number of audio data formats including: * * * * IS DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words are transmitted) MSB-First, left justified MSB-First, right justified
2
The interface can operate in master or slave modes.
CONTROL INTERFACES
To allow full software control over all features, the WM8985 offers a choice of 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Selection of the mode is via the MODE pin. In 2 wire mode, the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8985 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC and ADC. A flexible clock divider allows the 256fs DAC clock to be generated from a range of input clock frequencies, for example, 256fs, 384fs, 512fs and 768fs. A PLL is included which may be used to generate these clocks in the event that they are not available from the system controller. This PLL can accept a range of common input clock frequencies between 8MHz and 50MHz to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the GPIO1 pin and used elsewhere in the system; available in 2-wire control mode only.
POWER CONTROL
The design of the WM8985 has given much attention to power consumption without compromising performance. The WM8985 operates at low analog and digital supply voltages, and includes the ability to power off any unused parts of the circuitry under software control. It also includes standby and power off modes.
INPUT SIGNAL PATH
The WM8985 has a number of flexible analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to accommodate single-ended, pseudo-differential or dual differential microphones. There are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. A bypass path exists from the output of the boost/mix stage into the output left/right mixers.
MICROPHONE INPUTS
The WM8985 can accommodate a variety of microphone configurations including single ended and pseudo-differential inputs. The inputs to the left differential input PGA are LIN, LIP and L2. The inputs to the right differential input PGA are RIN, RIP and R2. In single-ended microphone input configuration the microphone signal should be input to LIN or RIN
w
PP, Rev 3.5, March 2007 28
Pre-Production and the non-inverting input of the input PGA clamped to VMID.
WM8985
Figure 12 Microphone Input PGA Circuit
The input PGAs are enabled by the INPPGAENL and INPPGAENR register bits. REGISTER ADDRESS R2 (02h) Power Management 2 2 BIT LABEL INPPGAENL DEFAULT 0 DESCRIPTION Left channel input PGA enable 0 = disabled 1 = enabled Right channel input PGA enable 0 = disabled 1 = enabled
3
INPPGAENR
0
Table 5 Input PGA Enable Register Settings
w
PP, Rev 3.5, January 2007 29
WM8985
REGISTER ADDRESS R44 (2Ch) Input Control BIT 0 LABEL LIP2INPPGA DEFAULT 1 DESCRIPTION
Pre-Production
Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) Connect LIN pin to left channel input PGA negative terminal. 0 = LIN not connected to input PGA 1 = LIN connected to input PGA amplifier negative terminal. Connect L2 pin to left channel input PGA positive terminal. 0 = L2 not connected to input PGA 1 = L2 connected to input PGA amplifier positive terminal (constant input impedance). Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) Connect RIN pin to right channel input PGA negative terminal. 0 = RIN not connected to input PGA 1 = RIN connected to right channel input PGA amplifier negative terminal. Connect R2 pin to right channel input PGA positive terminal. 0 = R2 not connected to input PGA 1 = R2 connected to input PGA amplifier positive terminal (constant input impedance).
1
LIN2INPPGA
1
2
L2_2INPPGA
0
4
RIP2INPPGA
1
5
RIN2INPPGA
1
6
R2_2INPPGA
0
Table 6 Input PGA Control
INPUT PGA VOLUME CONTROLS
The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always common and controlled by the register bits INPPGAVOLL[5:0] and INPPGABVOLR[5:0]. These register bits also affect the LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1 and the L2 pin when L2_2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically and the INPPGAVOLL and INPPGAVOLR bits should not be used.
w
PP, Rev 3.5, March 2007 30
Pre-Production
WM8985
REGISTER ADDRESS R45 (20h) Left channel input PGA volume control BIT 5:0 LABEL INPPGAVOLL DEFAULT 010000 (0dB) DESCRIPTION Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Mute control for left channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). Left channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Mute control for right channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). Right channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) ALC function select: 00 = ALC off 01 = ALC right only 10 = ALC left only 11 = ALC both on
6
INPPGAMUTEL
0
7
INPPGAZCL
0
8
INPPGAVU
Not latched
R46 (2Eh) Right channel input PGA volume control
5:0
INPPGAVOLR
010000 (0dB)
6
INPPGAMUTER
0
7
INPPGAZCR
0
8
INPPGAVU
Not latched
R32 (20h) ALC control 1
8:7
ALCSEL
00
Table 7 Input PGA Volume Control
w
PP, Rev 3.5, January 2007 31
WM8985
VOLUME UPDATES
Pre-Production
Volume settings will not be applied to the PGAs until a '1' is written to one of the INPPGAVU bits. This is to allow left and right channels to be updated at the same time, as shown in Figure 13.
Figure 13 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 14.
Figure 14 Click Noise During Volume Update In order to prevent this click noise, a zero cross function is provided. When enabled, this will cause the PGA volume to update only when a zero crossing occurs, minimising click noise as shown in Figure 15.
w
PP, Rev 3.5, March 2007 32
Pre-Production
WM8985
Figure 15 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8985 will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the INPPGAVU bit is set as shown in Figure 16.
Figure 16 Volume Update After Timeout
w
PP, Rev 3.5, January 2007 33
WM8985
AUXILLIARY INPUTS
Pre-Production
There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs or as a `beep' input signal to be mixed with the outputs. The AUXL/R inputs can be used as a line input to the input BOOST stage which has adjustable gain of -12dB to +6dB in 3dB steps, with an additional "off" state (i.e. not connected to ADC input). See the INPUT BOOST section for further details. The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB plus off.
INPUT BOOST
Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the L2/R2 input pin (can be used as a line input, bypassing the input PGA). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 17.
Figure 17 Input Boost Stage
w
PP, Rev 3.5, March 2007 34
Pre-Production
WM8985
The input PGA paths can have a +20dB boost (PGABOOSTL/R=1), a 0dB pass through (PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1).
REGISTER ADDRESS R47 (2Fh) Left Input BOOST control
BIT 8
LABEL PGABOOSTL
DEFAULT 1
DESCRIPTION Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
R48 (30h) Right Input BOOST control
8
PGABOOSTR
1
Table 8 Input BOOST Stage Control The Auxiliary amplifier path to the BOOST stages is controlled by the AUXL2BOOSTVOL[2:0] and AUXR2BOOSTVOL[2:0] register bits. When AUXL2BOOSTVOL/AUXR2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The L2/R2 path to the BOOST stage is controlled by the LIP2BOOSTVOL[2:0] and the RIP2BOOSTVOL[2:0] register bits. When L2_2BOOSTVOL[6:4] and R2_2BOOSTVOL[6:4]=000 the L2/R2 input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.
w
PP, Rev 3.5, January 2007 35
WM8985
REGISTER ADDRESS R42 (2Ah) OUT4 to ADC BIT 8:6 LABEL OUT4_2ADCVOL DEFAULT 000
Pre-Production
DESCRIPTION Controls the OUT4 to ADC input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain OUT4 to L or R ADC input 0 = Right ADC input 1 = Left ADC input Controls the auxiliary amplifier to the left channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain Controls the L2 pin to the left channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain Controls the auxiliary amplifier to the right channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain
5
OUT4_2LNR
0
R47 (2Fh) Left channel Input BOOST control
2:0
AUXL2BOOSTVOL
000
6:4
L2_2BOOSTVOL
000
R48 (30h) Right channel Input BOOST control
2:0
AUXR2BOOSTVOL
000
w
PP, Rev 3.5, March 2007 36
Pre-Production REGISTER ADDRESS BIT 6:4 LABEL R2_2BOOSTVOL DEFAULT 000
WM8985
DESCRIPTION Controls the R2 pin to the right channel input boost stage: 000 = Path disabled (disconnected) 001 = -12dB 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain
Table 9 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 (02h) Power management 2 BIT 4 LABEL BOOSTENL DEFAULT 0 DESCRIPTION Left channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Right channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON
5
BOOSTENR
0
Table 10 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD1 and when MBVSEL=1, MICBIAS=0.65*AVDD1. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS R1 (01h) Power management 1 BIT 4 LABEL MICBEN DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 11 Microphone Bias Enable Control
REGISTER ADDRESS R44 (2Ch) Input control
BIT 8
LABEL MBVSEL
DEFAULT 0
DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1
Table 12 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 18. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
w
PP, Rev 3.5, January 2007 37
WM8985
Pre-Production
Figure 18 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8985 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD1. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path for each ADC channel is illustrated in Figure 19.
Figure 19 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER ADDRESS R2 (02h) Power management 2 BIT 0 LABEL ADCENL DEFAULT 0 DESCRIPTION Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled PP, Rev 3.5, March 2007 38
1
ADCENR
0
Table 13 ADC Enable Control
w
Pre-Production
WM8985
The polarity of the output signal can also be changed under software control using the ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS R14 (0Eh) ADC Control BIT 0 LABEL ADCLPOL DEFAULT 0 DESCRIPTION ADC left channel polarity adjust: 0 = normal 1 = inverted ADC right channel polarity adjust: 0 = normal 1 = inverted ADC oversample rate select: 0 = 64x (lower power) 1 = 128x (best performance)
1
ADCRPOL
0
3
ADCOSR128
0
Table 14 ADC Control
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided and enabled as default. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 16.
REGISTER ADDRESS R14 (0Eh) ADC Control
BIT 6:4 7
LABEL HPFCUT HPFAPP
DEFAULT 000 0
DESCRIPTION Application mode cut-off frequency See Table 16 for details. Select audio mode or application mode 0 = Audio mode (1st order, fc = ~3.7Hz) nd 1 = Application mode (2 order, fc = HPFCUT) High Pass Filter Enable 0 = disabled 1 = enabled
8
HPFEN
1
Table 15 ADC Enable Control
HPFCUT [2:0] 8 000 001 010 011 100 101 110 111 82 102 131 163 204 261 327 408
SR=101/100 11.025 113 141 180 225 281 360 450 563 12 122 153 156 245 306 392 490 612 16 82 102 131 163 204 261 327 408
SR=011/010 fs (kHz) 22.05 113 141 180 225 281 360 450 563 24 122 153 156 245 306 392 490 612 32 82 102 131 163 204 261 327 408
SR=001/000 44.1 113 141 180 225 281 360 450 563 48 122 153 156 245 306 392 490 612
Table 16 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the SR register bits are set correctly for the actual sample rate as shown in Table 16. Sampling rate (SR) is enabled by register bits R7[1:3].
w
PP, Rev 3.5, January 2007 39
WM8985
PROGRAMMABLE NOTCH FILTER
Pre-Production
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup. REGISTER ADDRESS R27 (1Bh) Notch Filter 1 7 BIT 6:0 LABEL NFA0[13:7] NFEN DEFAULT 0 0 DESCRIPTION Notch Filter a0 coefficient, bits [13:7] Notch filter enable: 0 = Disabled 1 = Enabled 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R28 (1Ch) Notch Filter 2 6:0 8 NFA0[6:0] NFU 0 0 Notch Filter a0 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R29 (1Dh) Notch Filter 3 6:0 8 NFA1[13:7] NFU 0 0 Notch Filter a1 coefficient, bits [13:7] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R30 (1Eh) Notch Filter 4 0-6 8 NFA1[6:0] NFU 0 0 Notch Filter a1 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Table 17 Notch Filter Function The coefficients are calculated as follows:
a0 = 1 - tan( w b / 2) 1 + tan( w b / 2)
a1 = -(1 + a0 ) cos( w 0 )
Where:
w 0 = 2fc / fs w b = 2fb / fs
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212
w
PP, Rev 3.5, March 2007 40
Pre-Production
WM8985
NOTCH FILTER WORKED EXAMPLE
The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth. fc = 1000 Hz fb = 100 Hz fs = 48000 Hz
w 0 = 2fc / fs = 2 x (1000 / 48000) = 0.1308996939 rads w b = 2fb / fs = 2 x (100 / 48000) = 0.01308996939 rads
a0 =
1 - tan( w b / 2) 1 - tan(0.0130899693 9 / 2) = = 0.9869949627 1 + tan( w b / 2) 1 + tan( 0.0130899693 9 / 2)
a1 = -(1 + a0 ) cos( w 0 ) = -(1 + 0.9869949627 ) cos(0.1308996939 ) = -1.969995945
NFA0 = -a0 x 213 = -8085 (rounded to nearest whole number) NFA1 = -a1 x 212 = 8069 (rounded to nearest whole number)
These values are then converted to a 14-bit sign / magnitude notation: NFA0[13] = 1; NFA0[12:0] = 13'h1F95; NFA0 = 14'h3F95 = 14'b11111110010101 NFA1[13] = 0; NFA1[12:0] = 13'h1F85; NFA1 = 14'h1F85 = 14'b01111110000101
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from -127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: 0.5 x (G-255) dB for 1 G 255;
REGISTER ADDRESS BIT LABEL
MUTE for G = 0
DEFAULT DESCRIPTION
R15 (0Fh) Left channel ADC Digital Volume
7:0
ADCLVOL [7:0]
11111111 ( 0dB )
Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16) Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16)
8
ADCVU
Not latched 11111111 ( 0dB )
R16 (10h) Right channel ADC Digital Volume
7:0
ADCRVOL [7:0]
8
ADCVU
Not latched
Table 18 ADC Digital Volume Control
w
PP, Rev 3.5, January 2007 41
WM8985
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
Pre-Production
The WM8985 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level (ALCLVL). If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set by ALCATK. The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode. The ALC/limiter function is enabled by settings the register bits R32[8:7] ALCSEL.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R32 (20h) ALC Control 1
2:0
ALCMIN [2:0]
000 (-12dB)
Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB ALC function select 00 = ALC disabled 01 = Right channel ALC enabled 10 = Left channel ALC enabled 11 = Both channels ALC enabled ALC target - sets signal level at ADC input 1111 = -1.5dBFS 1110 = -1.5dBFS 1101 = -3dBFS 1100 = -4.5dBFS 1011 = -6dBFS 1010 = -7.5dBFS 1001 = -9dBFS 1000 = -10.5dBFS 0111 = -12dBFS 0110 = -13.5dBFS 0101 = -15dBFS 0100 = -16.5dBFS 0011 = -18dBFS 0010 = -19.5dBFS 0001 = -21dBFS PP, Rev 3.5, March 2007 42
5:3
ALCMAX [2:0]
111 (+35.25dB)
8:7
ALCSEL
00
R33 (21h) ALC Control 2
3:0
ALCLVL [3:0]
1011 (-6dB)
w
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
0000 = -22.5dBFS 7:4 ALCHLD [3:0] 0000 (0ms) ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or higher = 1.36s Determines the ALC mode of operation: 0 = ALC mode (Normal Operation) 1 = Limiter mode. Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 410us 820us 1.64ms Per 6dB 3.3ms 6.6ms 13.1ms 90% of range 24ms 48ms 192ms
R34 (22h) ALC Control 3
8
ALCMODE
0
7:4
ALCDCY [3:0]
0011 (13ms/6dB)
... (time doubles with every step) 420ms 3.36s 24.576s 1010 or higher 0011 (2.9ms/6dB) Decay (gain ramp-up) time (ALCMODE ==1) Per step 0000 0001 0010 90.8us 181.6us 363.2us Per 6dB 726.4us 1.453ms 2.905ms 90% of range 5.26ms 10.53 ms 21.06 ms 5.39s
... (time doubles with every step) 1010 3:0 ALCATK [3:0] 0010 (832us/6dB) 93ms 744ms ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 1010 or higher 0010 (182us/6dB) 104us 208us 416us 106ms Per 6dB 832us 1.66ms 3.32ms 852ms 90% of range 6ms 12ms 24.1ms 6.18s
... (time doubles with every step)
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 22.7us Per 6dB 182.4us 90% of range 1.31ms
w
PP, Rev 3.5, January 2007 43
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
0001 0010 1010
Table 20 ALC Control Registers
45.4us 90.8us 23.2ms
363.2us 726.4us 186ms
2.62ms 5.26ms 1.348s
... (time doubles with every step)
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.
NORMAL MODE
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this.
Figure 21 ALC Normal Mode Operation
w
PP, Rev 3.5, March 2007 44
Pre-Production
WM8985
In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at startup. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be the gain at switchover. The diagram below shows an example of limiter mode.
LIMITER MODE
Figure 20 ALC Limiter Mode Operation
ATTACK AND DECAY TIMES
The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants are shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs gain range. Note that, these times will vary slightly depending on the sample rate used (specified by the SR register).
w
PP, Rev 3.5, January 2007 45
WM8985
NORMAL MODE
Pre-Production
ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATK 104s 208s 416s 832s 1.66ms 3.33ms 6.66ms 13.3ms 26.6ms 53.2ms 106ms Attack Time (s) tATK6dB tATK90% 832s 6ms 1.66ms 12ms 3.33ms 24ms 6.66ms 48ms 13.3ms 96ms 26.6ms 192ms 53.2ms 384ms 106ms 767ms 213.2ms 1.53s 426ms 3.07s 852ms 6.13s
ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCY 410s 820s 1.64ms 3.28ms 6.56ms 13.1ms 26.2ms 52.5ms 105ms 210ms 420ms Decay Time (s) tDCY6dB tDCY90% 3.28ms 23.6ms 6.56ms 47.2ms 13.1ms 94.5ms 26.2ms 189ms 52.5ms 378ms 105ms 756ms 210ms 1.51s 420ms 3.02s 840ms 6.05s 1.68s 12.1s 3.36s 24.2s
Table 19 ALC Normal Mode (Attack and Decay times)
w
PP, Rev 3.5, March 2007 46
Pre-Production
WM8985
LIMITER MODE
ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATKLIM 22.7s 45.4S 90.8S 182S 363S 726S 1.45ms 2.9ms 5.81ms 11.6ms 23.2ms Attack Time (s) tATKLIM6dB tATKLIM90% 182s 1.31ms 363s 2.62ms 726s 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s
ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCYLIM 90.8s 182S 363S 726S 1.45ms 2.91ms 5.81ms 11.6ms 23.2ms 46.5ms 93ms Attack Time (s) tDCYLIM6dB tDCYLIM90% 726s 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s 372ms 2.68s 744ms 5.36s
Table 20 ALC Limiter Mode (Attack and Decay times)
w
PP, Rev 3.5, January 2007 47
WM8985
MINIMUM AND MAXIMUM GAIN
Pre-Production
The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R32 ALC Control 1
5:3 2:0
ALCMAX ALCMIN
111 000
Set Maximum Gain of PGA Set minimum gain of PGA
Table 23 ALC Max/Min Gain
In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level. ALCMIN sets the minimum gain value which can be applied to the signal.
Figure 23 ALC Min/Max Gain
ALCMAX 111 110 101 100 011 010 001 000
Maximum Gain (dB) 35.25 29.25 23.25 17.25 11.25 5.25 -0.75 -6.75
Table 24 ALC Max Gain Values
w
PP, Rev 3.5, March 2007 48
Pre-Production
WM8985
ALCMIN 000 001 010 011 100 101 110 111 Minimum Gain (dB) -12 -6 0 6 12 18 24 30
Table 25 ALC Min Gain Values
Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC starting gain is set between the ALCMAX and ALCMIN limits.
ALC HOLD TIME (NORMAL MODE ONLY)
In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins it's decay phase (gain increasing). The hold time is set by the ALCHLD register.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R33 ALC Control 2
7:4
ALCHLD
0000
ALC hold time before gain is increased.
Table 26 ALC Hold Time
If the hold time is exceeded this indicates that the signal has reached a new average level and the ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold during the hold period, the hold phase is abandoned and the ALC returns to normal operation.
w
PP, Rev 3.5, January 2007 49
WM8985
Pre-Production
Figure 24 ALCLVL
w
PP, Rev 3.5, March 2007 50
Pre-Production
WM8985
Figure 25 ALC Hold Time
ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
tHOLD (s) 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s
Table 27 ALC Hold Time Values
w
PP, Rev 3.5, January 2007 51
WM8985
PEAK LIMITER
Pre-Production
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.
NOISE GATE (NORMAL MODE ONLY)
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8985 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R35 (23h) ALC Noise Gate Control
2:0
NGTH
000
Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db 011 = -57dB 100 = -63dB 101 = -70dB 110 = -76dB 111 = -81dB Noise gate function enable 1 = enable 0 = disable
3
NGATEN
0
Table 28 ALC Noise Gate Control
The diagrams below show the response of the system to the same signal with and without noise gate.
w
PP, Rev 3.5, March 2007 52
Pre-Production
WM8985
Figure 21 ALC Operation Above Noise Gate Threshold
w
PP, Rev 3.5, January 2007 53
WM8985
Pre-Production
Figure 22 Noise Gate Operation
OUTPUT SIGNAL PATH
The WM8985 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled by register bits DACENL and DACENR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8985, irrespective of whether the DACs are running or not. The WM8985 DACs receive digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control Graphic equaliser A digital peak limiter Sigma-Delta Modulation High performance sigma-delta audio DAC converts the digital data into an analogue signal.
w
PP, Rev 3.5, March 2007 54
Pre-Production
WM8985
Figure 23 DAC Digital Filter Path
The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them to output different signals to the line outputs or back into the record path.
DIGITAL PLAYBACK (DAC) PATH
Digital data is passed to the WM8985 via the flexible audio interface and is then passed through a variety of advanced digital filters as shown in Figure 23 to the hi-fi DACs. The DACs are enabled by the DACENL/R register bits.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R3 (03h) Power Management 3
0
DACENL
0
Left channel DAC enable 0 = DAC disabled 1 = DAC enabled Right channel DAC enable 0 = DAC disabled 1 = DAC enabled
1
DACENR
0
Table 21 DAC Enable Control
The WM8985 also has a Soft Mute function, which when enabled, gradually attenuates the volume of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the SOFTMUTE bit to zero.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R10 (0Ah) DAC Control
0
DACPOL
0
Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Automute enable 0 = Amute disabled 1 = Amute enabled DAC oversampling rate: 0 = 64x (lowest power) 1 = 128x (best performance) Softmute enable: 0 = Enabled 1 = Disabled
1
DACRPOL
0
2
AMUTE
0
3
DACOSR128
0
6
SOFTMUTE
0
Table 22 DAC Control Register
w
PP, Rev 3.5, January 2007 55
WM8985
Pre-Production The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The DAC output phase defaults to non-inverted. Setting DACLPOL will invert the DAC output phase on the left channel and DACRPOL inverts the phase on the right channel.
AUTO-MUTE
The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is released as soon as a non-zero sample is detected. Auto-mute can be disabled using the AMUTE control bit.
DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain range is -127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 x (X-255) dB for 1 X 255;
REGISTER ADDRESS BIT LABEL
MUTE for X = 0
DEFAULT DESCRIPTION
R11 (0Bh) Left DAC Digital Volume
7:0
DACLVOL [7:0]
11111111 ( 0dB )
Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12)
8
DACVU
Not latched 11111111 ( 0dB )
R12 (0Ch) Right DAC Digital Volume
7:0
DACRVOL [7:0]
8
DACVU
Not latched
Table 23 DAC Digital Volume Control Note: An additional gain of up to 12dB can be added using the gain block embedded in the digital peak limiter circuit (see DAC OUTPUT LIMITER section).
5-BAND EQUALISER
A 5-band graphic equaliser function which can be used to change the output frequency levels to suit the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND EQUALISER section for further details on this feature.
3-D ENHANCEMENT
The WM8985 has an advanced digital 3-D enhancement feature which can be used to vary the perceived stereo separation of the left and right channels. Like the 5-band equaliser this feature can be applied to either the ADC record path or the DAC playback path but not both simultaneously. Refer to the 3-D STEREO ENHANCEMENT section for further details on this feature.
DAC DIGITAL OUTPUT LIMITER
The WM8985 has a digital output limiter function. The operation of this is shown in Figure 24. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
w
PP, Rev 3.5, March 2007 56
Pre-Production
WM8985
Figure 24 DAC Digital Limiter Operation
The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 24, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.
VOLUME BOOST
The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
w
PP, Rev 3.5, January 2007 57
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT
Pre-Production
DESCRIPTION
R24 (18h) DAC digital limiter control 1
3:0
LIMATK
0010
Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate. 0000 = 94us 0001 = 188s 0010 = 375us 0011 = 750us 0100 = 1.5ms 0101 = 3ms 0110 = 6ms 0111 = 12ms 1000 = 24ms 1001 = 48ms 1010 = 96ms 1011 to 1111 = 192ms
7:4
LIMDCY
0011
Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate: 0000 = 750us 0001 = 1.5ms 0010 = 3ms 0011 = 6ms 0100 = 12ms 0101 = 24ms 0110 = 48ms 0111 = 96ms 1000 = 192ms 1001 = 384ms 1010 = 768ms 1011 to 1111 = 1.536s Enable the DAC digital limiter: 0=disabled 1=enabled Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000 = 0dB 0001 = +1dB 0010 = +2dB 0011 = +3dB 0100 = +4dB 0101 = +5dB 0110 = +6dB 0111 = +7dB 1000 = +8dB 1001 = +9dB 1010 = +10dB 1011 = +11dB 1100 = +12dB 1101 to 1111 = reserved
8
LIMEN
0
R25 (19h) DAC digital limiter control 2
3:0
LIMBOOST
0000
w
PP, Rev 3.5, March 2007 58
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
6:4
LIMLVL
000
Programmable signal threshold level (determines level at which the limiter starts to operate) 000 = -1dB 001 = -2dB 010 = -3dB 011 = -4dB 100 = -5dB 101 to 111 = -6dB
Table 24 DAC Digital Limiter Control
5-BAND GRAPHIC EQUALISER
A 5-band graphic equaliser is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R18 (12h) EQ Control 1
8
EQ3DMODE
1
0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path
Table 25 EQ and 3D Enhancement DAC or ADC Path Select Note: The ADCs and DACs must be disabled before changing the EQ3DMODE bit.
The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB in 1dB steps). The peak filters have selectable bandwidth.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R18 (12h) EQ Band 1 Control
4:0 6:5
EQ1G EQ1C
01100 (0dB) 01
Band 1 Gain Control. See Table 31 for details. Band 1 Cut-off Frequency: 00 = 80Hz 01 = 105Hz 10 = 135Hz 11 = 175Hz
Table 26 EQ Band 1 Control
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R19 (13h) EQ Band 2 Control
4:0 6:5
EQ2G EQ2C
01100 (0dB) 01
Band 2 Gain Control. See Table 31 for details. Band 2 Centre Frequency: 00 = 230Hz 01 = 300Hz 10 = 385Hz 11 = 500Hz Band 2 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth
8
EQ2BW
0
Table 27 EQ Band 2 Control
w
PP, Rev 3.5, January 2007 59
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT
Pre-Production
DESCRIPTION
R20 (14h) EQ Band 3 Control
4:0 6:5
EQ3G EQ3C
01100 (0dB) 01
Band 3 Gain Control. See Table 31 for details. Band 3 Centre Frequency: 00 = 650Hz 01 = 850Hz 10 = 1.1kHz 11 = 1.4kHz Band 3 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth
8
EQ3BW
0
Table 28 EQ Band 3 Control
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R21 (15h) EQ Band 4 Control
4:0 6:5
EQ4G EQ4C
01100 (0dB) 01
Band 4 Gain Control. See Table 31 for details Band 4 Centre Frequency: 00 = 1.8kHz 01 = 2.4kHz 10 = 3.2kHz 11 = 4.1kHz Band 4 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth
8
EQ4BW
0
Table 29 EQ Band 4 Control
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R22 (16h) EQ Band 5 Gain Control
4:0 6:5
EQ5G EQ5C
01100 (0dB) 01
Band 5 Gain Control. See Table 31 for details. Band 5 Cut-off Frequency: 00 = 5.3kHz 01 = 6.9kHz 10 = 9kHz 11 = 11.7kHz
Table 30 EQ Band 5 Control
GAIN REGISTER
GAIN
00000 00001 00010 .... (1dB steps) 01100 01101 11000 11001 to 11111
Table 31 Gain Register Table
+12dB +11dB +10dB 0dB -1dB -12dB Reserved
See also Figure 46 to Figure 63 for equaliser and high pass filter filter responses.
w
PP, Rev 3.5, March 2007 60
Pre-Production
WM8985
The WM8985 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when both ADCs and both DACs are disabled. The DEPTH3D setting controls the degree of stereo expansion.
3D STEREO ENHANCEMENT
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R41 (29h) 3D Control
3:0
DEPTH3D
0000
Stereo depth 0000 = Disabled 0001 = 6.67% 0010 = 13.3% 0011 = 20% 0100 = 26.7% 0101 = 33.3% 0110 = 40% 0111 = 46.6% 1000 = 53.3% 1001 = 60% 1010 = 66.7% 1011 = 73.3% 1100 = 80% 1101 = 86.7% 1110 = 93.3% 1111 = 100% (maximum 3D effect)
Table 32 3D Stereo Enhancement Function Note: When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting.
ANALOGUE OUTPUTS
The WM8985 has three sets of stereo analogue outputs. These are: * * * LOUT1 and ROUT1 which are normally used to drive a headphone load. LOUT2 and ROUT2 - which can be used as class D or class AB headphone drivers. OUT3 and OUT4 - can be configured as a stereo line out (OUT3 is left output and OUT4 is right output) or a differential output. OUT4 can also be used to provide a mono mix of left and right channels.
The outputs LOUT2 and ROUT2 are powered from AVDD2 and are capable of driving a 1V rms signal (AVDD1/3.3). LOUT1, ROUT1, OUT3 and OUT4 are powered from AVDD1 LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB gain ranges. There are four output mixers in the output signal path, the left and right channel mixers which control the signals to headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4 mixers.
w
PP, Rev 3.5, January 2007 61
WM8985
LEFT AND RIGHT OUTPUT CHANNEL MIXERS
Pre-Production
The left and right output channel mixers are shown in Figure 25. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This allows a mono mix of the DAC channels to be performed as well as mixing in external line-in from the AUX or speech from the input bypass path. The AUX and bypass inputs have individual volume control from -15dB to +6dB and the DAC volume can be adjusted in the digital domain if required. The output of these mixers is connected to both the headphone (LOUT1 and ROUT1) and class D headphone (LOUT2 and ROUT2) and can optionally be connected to the OUT3 and OUT4 mixers.
Figure 25 Left/Right Output Channel Mixers
w
PP, Rev 3.5, March 2007 62
Pre-Production
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R43 (2Bh) Output mixer control
8
BYPL2RMIX
0
Left bypass path (from the Left channel input PGA stage) to right output mixer 0 = not selected 1 = selected Right bypass path (from the right channel input PGA stage) to Left output mixer 0 = not selected 1 = selected Right DAC output to left output mixer 0 = not selected 1 = selected Left DAC output to right output mixer 0 = not selected 1 = selected Left DAC output to left output mixer 0 = not selected 1 = selected Left bypass path (from the left channel input PGA stage) to left output mixer 0 = not selected 1 = selected Left bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Left Auxiliary input to left channel output mixer: 0 = not selected 1 = selected Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB
R43 (2Bh) Output mixer control
7
BYPR2LMIX
0
R49 (31h) Output mixer control
5
DACR2LMIX
0
6
DACL2RMIX
0
R50 (32h) Left channel output mixer control
0
DACL2LMIX
1
1
BYPL2LMIX
0
4:2
BYPLMIXVOL
000
5
AUXL2LMIX
0
8:6
AUXLMIXVOL
000
w
PP, Rev 3.5, January 2007 63
WM8985
R51 (33h) Right channel output mixer control 0 DACR2RMIX 1
Pre-Production Right DAC output to right output mixer 0 = not selected 1 = selected Right bypass path (from the right channel input PGA stage) to right output mixer 0 = not selected 1 = selected Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Right Auxiliary input to right channel output mixer: 0 = not selected 1 = selected Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Left output channel mixer enable: 0 = disabled 1= enabled Right output channel mixer enable: 0 = disabled 1 = enabled
1
BYPR2RMIX
0
4:2
BYPRMIXVOL
000
5
AUXR2RMIX
0
8:6
AUXRMIXVOL
000
R3 (03h) Power management 3
2
LMIXEN
0
3
RMIXEN
0
Table 33 Left and Right Output Mixer Control
HEADPHONE OUTPUTS (LOUT1 AND ROUT1)
The headphone outputs LOUT1 and ROUT1 can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC-coupled to a buffered midrail reference (LOUT2 or ROUT2), saving a capacitor (capless mode). When using capless mode AVDD1 and AVDD2 should use the same supply to maximise supply rejection. OUT3 and OUT4 should not be used as a buffered midrail reference in capless mode.
w
PP, Rev 3.5, March 2007 64
Pre-Production
Headphone Output using DC Blocking Capacitors
WM8985
DC Coupled Headphone Output
Figure 26 Recommended Headphone Output Configurations
When DC blocking capacitors are used, their capacitance and the load resistance together determine the lower cut-off frequency of the output signal, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1, C2 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone pseudo-ground is connected to the buffered midrail reference pin (LOUT2 or ROUT2). The L/ROUT2 pins can be configured as a DC output driver by setting the LOUT2MUTE and ROUT2MUTE register bits. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. It is not recommended to use DC-coupling to line inputs of another device. Although the built-in short circuit protection on the headphone outputs would be tolerant of shorts to ground, such a connection could be noisy, and may not function properly if the other device is grounded. DC-coupled configurations should only be used with headphones.
w
PP, Rev 3.5, January 2007 65
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT
Pre-Production
DESCRIPTION
R52 (34h) LOUT1 Volume control
5:0
LOUT1VOL
111001 (0dB)
Left headphone output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Left headphone output mute: 0 = Normal operation 1 = Mute Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53) Right headphone output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Right headphone output mute: 0 = Normal operation 1 = Mute Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53)
6
LOUT1MUTE
0
7
LOUT1ZC
0
8
HPVU
Not latched
R53 ROUT1 Volume control
5:0
ROUT1VOL
111001 (0dB)
6
ROUT1MUTE
0
7
ROUT1ZC
0
8
HPVU
Not latched
Table 34 OUT1 Volume Control
w
PP, Rev 3.5, March 2007 66
Pre-Production
WM8985
CLASS D / CLASS AB HEADPHONE OUTPUTS (LOUT2 AND ROUT2)
The outputs LOUT2 and ROUT2 are designed to drive two headphone loads of 16 or 32 or line outputs (See Headphone Output and Line Output sections, respectively). Each output has an individual volume control PGA, a mute and an enable control bit as shown in Figure 27. LOUT2 and ROUT2 output the left and right channel mixer outputs respectively.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R7 (07h)
7:4
DCLKDIV
1000
Controls clock division from SYSCLK to generate suitable class D clock. Recommended class D clock frequency = 1.4MHz. 0000 = divide by 1 0010 = divide by 2 0011 = divide by 3 0100 = divide by 4 0101 = divide by 5.5 0110 = divide by 6 1000 = divide by 8 1001 = divide by 12 1010 = divide by 16 Enable signal for class D mode on LOUT2 and ROUT2 0 = Class AB mode 1 = Class D mode
R23 (17h)
8
CLASSDEN
0
Table 35 Class D Control Registers
When driving headphones using class D outputs it is necessary to use appropriate filtering, placed close to the device, to minimise EMI emissions from the headphone cable (Refer to "Applications Information" for more information). This filtering does not prevent class AB mode operation.
Figure 27 LOUT2 and ROUT2 Class D Headphone Configuration
w
PP, Rev 3.5, January 2007 67
WM8985
Pre-Production
Figure 28 LOUT2 and ROUT2 Class AB Headphone Configuration
The output configurations shown in figures 29 and 30 are both suitable for class AB operation. The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the bypass path (output of the input boost stage) and the AUX input. The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over 0dB may cause clipping if the input signal is too high. The LOUT2MUTE/ ROUT2MUTE register bits cause these outputs to be muted (the output DC level is driven out). The output pins remain at the same DC level, so that no click noise is produced when muting or un-muting.
w
PP, Rev 3.5, March 2007 68
Pre-Production
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R54 (36h) LOUT2 Volume control
5:0
LOUT2VOL
111001
Left output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Left output mute: 0 = Normal operation 1 = Mute LOUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) Right output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Right output mute: 0 = Normal operation 1 = Mute ROUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55)
6
LOUT2MUTE
0
7
LOUT2ZC
0
8
OUT2VU
Not latched
R55 (37h) ROUT2 Volume control
5:0
ROUT2VOL
111001
6
ROUT2MUTE
0
7
ROUT2ZC
0
8
OUT2VU
Not latched
Table 36 OUT2 Volume Control
ZERO CROSS TIMEOUT
A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * SYSCLK period.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R7 (07h) Additional Control
0
SLOWCLKEN
0
Slow clock enable 0 = slow clock disabled 1 = slow clock enabled
Table 37 Timeout Clock Enable Control Note: SLOWCLKEN is also used for the jack insert detect debounce circuit
w
PP, Rev 3.5, January 2007 69
WM8985
OUT3/OUT4 MIXERS AND OUTPUT STAGES
Pre-Production
The OUT3/OUT4 pins provide an additional stereo line output, a mono output, or a differential output. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 29. The OUT3 and OUT4 output stages are powered from AVDD1 and AGND1.
Figure 29 OUT3 and OUT4 Mixers
OUT3 can provide a left line output, or a mono mix line output. OUT4 can provide a right line output, or a mono mix line output. A 6dB attenuation function is provided for OUT4, to prevent clipping during mixing of left and right signals. This function is enabled by the OUT4ATTN register bit.
w
PP, Rev 3.5, March 2007 70
Pre-Production
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R56 (38h) OUT3 mixer control
6 3
OUT3MUTE OUT4_2OUT3
0 0
0 = Output stage outputs OUT3 mixer 1 = Output stage muted OUT4 mixer output to OUT3 0 = disabled 1 = enabled Left ADC input to OUT3 0 = disabled 1 = enabled Left DAC mixer to OUT3 0 = disabled 1 = enabled Left DAC output to OUT3 0 = disabled 1 = enabled OUT3 mixer output to OUT4 0 = disabled 1 = enabled 0 = Output stage outputs OUT4 mixer 1 = Output stage muted 0 = OUT4 normal output 1 = OUT4 attenuated by 6dB Left DAC mixer to OUT4 0 = disabled 1 = enabled Left DAC to OUT4 0 = disabled 1 = enabled Right ADC input to OUT4 0 = disabled 1 = enabled Right DAC mixer to OUT4 0 = disabled 1 = enabled Right DAC output to OUT4 0 = disabled 1 = enabled
2
BYPL2OUT3
0
1
LMIX2OUT3
0
0
LDAC2OUT3
1
R57 (39h) OUT4 mixer control
7
OUT3_2OUT4
0
6 5 4
OUT4MUTE OUT4ATTN LMIX2OUT4
0 0 0
3
LDAC2OUT4
0
2
BYPR2OUT4
0
1
RMIX2OUT4
0
0
RDAC2OUT4
1
Table 38 OUT3/OUT4 Mixer Registers
w
PP, Rev 3.5, January 2007 71
WM8985
ENABLING THE OUTPUTS
Pre-Production
Each analogue output of the WM8985 can be independently enabled or disabled. The analogue mixer associated with each output has a separate enable bit. All outputs are disabled by default. To save power, unused parts of the WM8985 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see "Power Management" and "Applications Information" sections).
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R1 (01h) Power Management 1 R2 (02h) Power Management 2 R3 (03h) Power Management 3
2 6 7 8 7 6
BUFIOEN OUT3MIXEN OUT4MIXEN ROUT1EN LOUT1EN SLEEP
0 0 0 0 0 0
Unused input/output bias buffer enable OUT3 mixer enable OUT4 mixer enable ROUT1 output enable LOUT1 output enable 0 = Normal device operation 1 = Supply current reduced in device standby mode when clock supplied Left mixer enable Right mixer enable LOUT2 output enable ROUT2 output enable OUT3 enable OUT4 enable
2 3 5 6 7 8
LMIXEN RMIXEN LOUT2EN ROUT2EN OUT3EN OUT4EN
0 0 0 0 0 0
Note: All "Enable" bits are 1 = ON, 0 = OFF Table 39 Output Stages Power Management Control
THERMAL SHUTDOWN
To protect the WM8985 from becoming too hot, a thermal sensor has been built in. If the device junction temperature reaches approximately 125C and the TSDEN and TSOPCTRL bit are set, then all outputs will be disabled to avoid further increase of the chip temperature. Additionally, when the device is too hot and TSDEN is set, then the WM8985 de-asserts GPIO bit 11, a virtual GPIO that can be set up to generate an interrupt to the CPU (see "GPIO and Interrupt Control" section).
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R49 (31h) Output Control
1
TSDEN
0
Thermal Sensor Enable 0 = disabled 1 = enabled Thermal Shutdown Output enable 0 = Disabled 1 = Enabled, i.e. all outputs will be disabled if TI set and the device junction temperature is more than 125C.
2
TSOPCTRL
0
Table 40 Thermal Shutdown
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (AVDD1/2) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30k.
w
PP, Rev 3.5, March 2007 72
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
R49 (31h)
0
VROI
0
VREF (AVDD1/2) to analogue output resistance 0 = approx 1k 1 = approx 30 k
Table 41 Disabled Outputs to VREF Resistance
A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This buffer can be enabled using the BUFIOEN register bit. Figure 30 summarises the bias options for the output pins.
Analogue inputs
1k
1k
1k 1k
LOUT1
30k
VROI R49[0]
1k
ROUT1
30k
AVDD/2
+
AVDD/2
VROI R49[0]
BUFIOEN R1[2] Used to tie off all unused inputs and outputs
1k
OUT4
30k
VROI R49[0]
1k
OUT3
30k
VROI R49[0]
1k
LOUT2
30k
VROI R49[0]
1k
ROUT2
30k
VROI R49[0]
Figure 30 Unused Input/Output Pin Tie-off Buffers L/ROUT2EN/ OUT3/4EN VROI OUTPUT CONFIGURATION
0 0 1
0 1 X
1k to AVDD1/2 30k to AVDD1/2 Output enabled (DC level=AVDD1/2)
Table 42 Unused Output Pin Bias Options
w
PP, Rev 3.5, January 2007 73
WM8985
DIGITAL AUDIO INTERFACES
The audio interface has four pins: * * * * ADCDAT: ADC data output DACDAT: DAC data input LRC: Data Left/Right alignment clock BCLK: Bit clock, for synchronisation
Pre-Production
The clock signals BCLK, and LRC can be outputs when the WM8985 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: * * * * * Left justified Right justified I 2S DSP mode A DSP mode B
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8985 audio interface may be configured as either master or slave. As a master interface device the WM8985 generates BCLK and LRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8985 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
Figure 31 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRC transition.
w
PP, Rev 3.5, March 2007 74
Pre-Production
WM8985
Figure 32 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 33 I2S Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the LRC pulse shown in Figure 34 and Figure 35. In device slave mode, Figure 36 and Figure 37, it is possible to use any length of LRC pulse less than 1/fs, providing the falling edge of the LRC pulse occurs greater than one BCLK period before the rising edge of the next LRC pulse.
Figure 34 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
w
PP, Rev 3.5, January 2007 75
WM8985
Pre-Production
Figure 35 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
Figure 36 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
Figure 37 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)
w
PP, Rev 3.5, March 2007 76
Pre-Production
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R4 (04h) Audio Interface Control
0
MONO
0
Selects between stereo and mono device operation: 0 = Stereo device operation 1 = Mono device operation. Data appears in `left' phase of LRC only. Controls whether ADC data appears in `right' or `left' phases of LRC clock: 0 = ADC left data appear in `left' phase of LRC and right data in 'right' phase 1 = ADC left data appear in `right' phase of LRC and right data in 'left' phase Controls whether DAC data appears in `right' or `left' phases of LRC clock: 0 = DAC left data appear in `left' phase of LRC and right data in 'right' phase 1 = DAC left data appear in `right' phase of LRC and right data in 'left' phase Audio interface Data Format Select: 00 = Right Justified 01 = Left Justified 10 = I2S format 11 = DSP/PCM mode Word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits (see note) LRC clock polarity 0 = normal 1 =inverted DSP Mode - mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) st 1 = MSB is available on 1 BCLK rising edge after LRC rising edge (mode B)
1
ALRSWAP
0
2
DLRSWAP
0
4:3
FMT
10
6:5
WL
10
7
LRP
0
8
BCP
0
BCLK polarity 0 = normal 1 = inverted Digital loopback function 0 = No loopback 1 = Loopback enabled, ADC data output is fed directly into DAC data input.
R5
0
LOOPBACK
0
Table 43 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode.
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised below. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and LRC are outputs. The frequency of BCLK in master mode can be controlled with BCLKDIV. The frequencies of BCLK and LRC are also controlled by MCLKDIV. The LRC sample rate is set to the required values by MCLKDIV and the BCLK rate will be set accordingly to provide sufficient BCLKs for that chosen sample rate. These clocks are divided down versions of master clock.
w
PP, Rev 3.5, January 2007 77
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT
Pre-Production
DESCRIPTION
R6 (06h) Clock Generation Control
0
MS
0
Sets the chip to be master over LRC and BCLK 0 = BCLK and LRC clock are inputs 1 = BCLK and LRC clock are outputs generated by the WM8985 (MASTER) Configures the BCLK output frequency, for use when the chip is master over BCLK. 000 = divide by 1 (BCLK=SYSCLK) 001 = divide by 2 (BCLK=SYSCLK/2) 010 = divide by 4 (BCLK=SYSCLK/4) 011 = divide by 8 (BCLK=SYSCLK/8) 100 = divide by 16 (BCLK=SYSCLK/16) 101 = divide by 32 (BCLK=SYSCLK/32) 110 = reserved 111 = reserved Sets the scaling for SYSCLK clock output (under control of CLKSEL) 000 = divide by 1 (LRC=SYSCLK/128) 001 = divide by 1.5 (LRC=SYSCLK/192) 010 = divide by 2 (LRC=SYSCLK/256) 011 = divide by 3 (LRC=SYSCLK/384) 100 = divide by 4 (LRC=SYSCLK/512) 101 = divide by 6 (LRC=SYSCLK/768) 110 = divide by 8 (LRC=SYSCLK/1024) 111 = divide by 12 (LRC=SYSCLK/1536) Controls the source of the clock for all internal operation: 0 = MCLK 1 = PLL output
4:2
BCLKDIV
000
7:5
MCLKDIV
010
8
CLKSEL
1
Table 44 Clock Control
AUDIO SAMPLE RATES
The WM8985 ADC high pass filter, ALC and DAC limiter characteristics are sample rate dependent. SR should be set to the correct sample rate or the closest value if the actual sample rate is not available. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen. The filter characteristics and the ALC attack decay and hold times will scale appropriately.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R7 (07h) Additional Control
3:1
SR
000
Approximate sample rate (configures the coefficients for the internal digital filters): 000 = 48kHz 001 = 32kHz 010 = 24kHz 011 = 16kHz 100 = 12kHz 101 = 8kHz 110-111 = reserved
Table 45 Sample Rate Control
w
PP, Rev 3.5, March 2007 78
Pre-Production
WM8985
The WM8985 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8985 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from an existing audio master clock. Figure shows the PLL and internal clocking on the WM8985. The PLL can be enabled or disabled by the PLLEN register bit.
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1 (01h) Power management 1
5
PLLEN
0
PLL enable 0 = PLL off 1 = PLL on
Table 46 PLLEN Control Bit
Figure 38 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure ) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (224 (R-PLLN))
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement. Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 PLLN = int R = 8 k = int ( 224 x (8.192 - 8)) = 3221225 = 3126E9h
w
PP, Rev 3.5, January 2007 79
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT
Pre-Production
DESCRIPTION
R36 (24h) PLL N value
4
PLLPRESCALE
0
0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input to PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
3:0
PLLN
1000
R37 (25h) PLL K value 1 R38 (26h) PLL K Value 2 R39 (27h) PLL K Value 3
5:0
PLLK [23:18]
0Ch
8:0
PLLK [17:9]
093h
8:0
PLLK [8:0]
0E9h
Table 47 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in 48.
PLLPRESCALE
MCLKDIV
MCLK (MHz) (f1)
DESIRED OUTPUT (SYSCLK) (MHz)
f2 (MHz)
R
N
K
N REGISTER R36[3:0]
K REGISTERS R37 R38 R39
12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27
11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288
90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304
1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778
7h 8h 6h 7h 6h 6h 9h Ah 9h 9h 9h 9h 7h 8h 6h 7h 6h 7h
86C226h 3126E8h F28BD4h 8FD525h 45A1CAh D3A06Eh 6872AFh 3D70A3h 2DB492h FD809Fh 1F76F7h EE009Eh 86C226h 3126E8h F28BD4h 8FD525h B0AC93h 482296h
XX7h XX8h XX6h XX7h XX6h XX6h XX9h XXAh XX9h XX9h XX9h XX9h XX7h XX8h XX6h XX7h XX6h XX7h
021h 00Ch 03Ch 023h 011h 034h 01Ah 00Fh 00Bh 03Fh 007h 03Bh 021h 00Ch 03Ch 023h 02Ch 012h
161h 093h 145h 1EAh 0D0h 1D0h 039h 0B8h 0DAh 0C0h 1BBh 100h 161h 093h 145h 1EAh 056h 011h
026h 0E8h 1D4h 125h 1CAh 06Eh 0AFh 0A3h 092h 09Fh 0F7h 09Eh 026h 0E8h 1D4h 125h 093h 096h
Table 48 PLL Frequency Examples
w
PP, Rev 3.5, March 2007 80
Pre-Production
WM8985
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8985 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R5 (05h) Companding Control
2:1
ADC_COMP
0
ADC companding 00 = off 01 = reserved 10 = -law 11 = A-law DAC companding 00 = off 01 = reserved 10 = -law 11 = A-law 0 = off 1 = device operates in 8-bit mode.
4:3
DAC_COMP
0
5
WL8
0
Table 49 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x 1/A } for 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to use 8 BCLK's per LRC frame. When using DSP mode B, this allows 8-bit data words to be output consecutively every 8 BCLK's and can be used with 8-bit data words using the A-law and u-law companding functions.
BIT7 BIT[6:4] BIT[3:0]
SIGN
EXPONENT
MANTISSA
Table 50 8-bit Companded Word Composition
w
PP, Rev 3.5, January 2007 81
WM8985
u-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input
Pre-Production
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 39 -Law Companding
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 40 A-Law Companding
w
PP, Rev 3.5, March 2007 82
Pre-Production
WM8985
The WM8985 has three dual purpose input/output pins. * * * CSB/GPIO1: CSB / GPIO1 pin L2/GPIO2: Left channel line input / headphone detection input R2/GPIO3: Right channel line input / headphone detection input
GENERAL PURPOSE INPUT/OUTPUT
The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 function is provided for use as jack detection input or general purpose output. The default configuration for the CSB/GPIO1 is to be an input. When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection, depending on how the MODE pin is set. Table 45 illustrates the functionality of the GPIO1 pin when used as a general purpose output.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h) GPIO Control
2:0
GPIO1SEL
000
CSB/GPIO1 pin function select: 000 = input (CSB / Jack detection: depending on MODE setting) 001 = reserved 010 = Temp ok 011 = Amute active 100 = PLL clk output 101 = PLL lock 110 = logic 0 111 = logic 1 GPIO1 Polarity invert 0 = Non inverted 1 = Inverted PLL Output clock division ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 GPIO1 Internal pull-down enable: 0 = Internal pull-down disabled 1 = Internal pull-down enabled GPIO1 Internal pull-up enable: 0 = Internal pull-up disabled 1 = Internal pull-up enabled GPIO1 Open drain enable 0 = Open drain disabled 1 = Open drain enabled
3
GPIO1POL
0
5:4
OPCLKDIV
00
6
GPIO1GPD
0
7
GPIO1GPU
0
8
GPIO1GP
0
Table 45 CSB/GPIO Control Note:
If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the GPIO1SEL[2:0] bits.
w
PP, Rev 3.5, January 2007 83
WM8985
Pre-Production
For further details of the jack detect operation see the OUTPUT SWITCHING section.
OUTPUT SWITCHING (JACK DETECT)
When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch control input to automatically disable one set of outputs and enable another; the most common use for this functionality is as jack detect circuitry. The L2/GPIO2 and R2/GPIO3 pins can also be used for this purpose. The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a slow clock with period 221 x MCLK and is enabled by the SLOWCLKEN bit.
Notes:
1. 2.
The SLOWCLKEN bit must be enabled for the jack detect circuitry to operate. The GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which is used
Switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are the output enable signals which are used if the selected jack detection pin is at logic 0 (after debounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce). The jack detection enables operate as follows: All OUT_EN signals have an AND function performed with their normal enable signals (in Table 39). When an output is normally enabled as per Table 39, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0; it will turn the output off. If the normal enable signal is already OFF (0), the jack detection signal will have no effect due to the AND function. During jack detection if the user desires an output to be un-changed whether the jack is in or not, both the JD_EN settings, i.e. JD_EN0 and JD_EN1, should be set to 0000. If jack detection is not enabled (JD_EN=0), the output enables default to all 1's, allowing the outputs to be controlled as normal via the normal output enables found in Table 39.
w
PP, Rev 3.5, March 2007 84
Pre-Production
WM8985
BIT REGISTER ADDRESS LABEL DEFAULT DESCRIPTION
R9 (09h) GPIO control
5:4
JD_SEL
00
Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved Jack Detection Enable 0 = disabled 1 = enabled Output enables when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 Output enables when selected jack detection input is logic 1 [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1
6
JD_EN
0
R13 (00h)
3:0
JD_EN0
0000
7:4
JD_EN1
0000
Table 46 Jack Detect Register Control Bits
CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire control interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 47. The WM8985 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are register address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 data bits in each control register.
MODE INTERFACE FORMAT
Low High
2 wire 3 wire
Table 47 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits.
Figure 38 3-Wire Serial Control Interface
w
PP, Rev 3.5, January 2007 85
WM8985
2-WIRE SERIAL CONTROL MODE
Pre-Production
The WM8985 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8985). The WM8985 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8985, the WM8985 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8985 returns to the idle condition and waits for a new start condition and valid address. During a write, once the WM8985 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8985 register address plus the first bit of register data). The WM8985 then acknowledges the first data byte by driving SDIN low for one clock cycle. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8985 acknowledges again by pulling SDIN low. Transfer is complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8985 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the control interface returns to the idle condition.
SDIN
DEVICE ADDRESS (7 BITS)
RD / WR BIT
ACK (LOW)
CONTROL BYTE 1 (BITS 15 TO 8)
ACK (LOW)
CONTROL BYTE 1 (BITS 7 TO 0)
ACK (LOW)
SCLK START STOP
register address and 1st register data bit
remaining 8 bits of register data
Figure 39 2-Wire Serial Control Interface
In 2-wire mode the WM8985 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8985 can be reset by performing a write of any value to the software reset register (address 0h). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are initially set to default when the device is powered up.
POWER SUPPLIES
The WM8985 requires four separate power supplies: AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and output drivers LOUT1, ROUT1, OUT3 and OUT4. AVDD1 must be between 2.5V and 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphones). Higher AVDD1 will improve audio quality. AVDD2 and AGND2: Output driver supplies, power LOUT2 and ROUT2. AVDD2 must be between 2.5V and 3.6V. AVDD2 can be tied to AVDD1, but it requires separate layout and decoupling capacitors to curb harmonic distortion. DCVDD: Digital core supply, powers all digital functions except the audio and control interface pads. DCVDD must be between 1.71V and 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD must be between 1.71V and 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths.
w
PP, Rev 3.5, March 2007 86
Pre-Production
WM8985
POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR128 and DACOSR128 the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R10 (0Ah) DAC control R14 (0Eh) ADC control
3
DACOSR128
0
DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR)
3
ADCOSR128
0
Table 48 ADC and DAC Oversampling Rate Selection
LOW POWER MODE
If only DAC or ADC functionality is required, the WM8985 can be put into a low power mode. In this mode, the DSP core runs at half of the normal rate, reducing digital power consumption of the core by half. For DAC low power only, 3D enhancement with 2-Band equaliser functionality is permitted, where only Band 1 (low shelf) and Band 5 (high shelf) can be used. For ADC low power, the equaliser and 3D cannot be used.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h) Additional Ctrl
8
M128ENB
0
0 = low power mode enabled 1 = low power mode disabled
Table 49 DSP Core Low Power Mode Control
There are 3 modes of low power operation, as detailed below. The device will not enter low power unless in one of these register configurations, regardless of M128ENB. For pop-free operation of the device it is recommended to change the M128ENB low power functionality only when both the DACs and ADCs are disabled, i.e. when DACENL=0, DACENR=0, ADCENL=0 and ADCENR=0.
FUNCTION
REGISTER BITS
SETTING
DESCRIPTION
ADC low power
M128ENB ADCENL ADCENR DACENL DACENR EQ3DMODE M128ENB ADCENL ADCENR DACENL DACENR
0 1 1 0 0 1 (DAC path) 0 0 0 1 1
Either or both of ADCENL and ADCENR must be set (mono or stereo mode)
DAC low power
Either or both of DACENL and DACENR must be set (mono or stereo mode) EQ3DMODE = 0: EQ in ADC path EQ3DMODE = 1: EQ in DAC path
Table 50 DSP Core Low Power Modes for ADC Only and DAC Only Modes
w
PP, Rev 3.5, January 2007 87
WM8985
VMID
Pre-Production
The analogue circuitry will not operate unless VMID is enabled. The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R1 (01h) Power management 1
1:0
VMIDSEL
00
Reference string impedance to VMID pin 00 = off (250k VMID to AGND1) 01=75k 10=300k 11=5k
Table 51 VMID Impedance Control
BIASEN
The analogue amplifiers will not operate unless BIASEN is enabled.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R1 (01h) Power management 1
3
BIASEN
0
Analogue amplifier bias control 0 = disabled 1 = enabled
Table 52 Analogue Bias Control
w
PP, Rev 3.5, March 2007 88
Pre-Production
WM8985
REGISTER MAP
ADDR B[15:9] DEC HEX REGISTER NAME Software Reset Power manage't 1 Power manage't 2 Power manage't 3 Audio Interface Companding ctrl Clock Gen ctrl Additional ctrl GPIO Stuff Jack detect control DAC Control Left DAC digital Vol Right DAC dig'l Vol ADC Control Left ADC Digital Vol Right ADC Digital Vol EQ1 - low shelf EQ2 - peak 1 EQ3 - peak 2 EQ4 - peak 3 EQ5 - high shelf Class D Control DAC Limiter 1 DAC Limiter 2 Notch Filter 1 Notch Filter 2 Notch Filter 3 Notch Filter 4 ALC control 1 ALC control 2 ALC control 3 Noise Gate PLL N PLL K 1 PLL K 2 PLL K 3 3D control OUT4 to ADC Beep control OUT4_2ADCVOL[2:0] BYPL2 RMIX BYPR2 LMIX 0 OUT4_2 LNR 0 0 0 0 0 CLKSEL M128ENB GPIO1GP 0 0 DACVU DACVU 0 HPFEN ADCVU ADCVU EQ3DMODE EQ2BW EQ3BW EQ4BW 0 CLASSDEN LIMEN 0 NFU NFU NFU NFU ALCSEL[1:0] 0 ALCMODE 0 0 0 0 0 0 0 NFEN 0 0 0 0 ALCHLD[3:0] ALCDCY[3:0] 0 0 0 PLLK[17:9] PLLK[8:0] DEPTH3D[3:0] POBCTRL 0 0 0 0 0 0 0 0 PLLPRE SCALE PLLK[23:18] NGEN ALCMAX[2:0] 0 0 0 0 0 0 0 EQ1C[1:0] EQ2C[1:0] EQ3C[1:0] EQ4C[1:0] EQ5C[1:0] 0 LIMLVL[2:0] NFA0[13:7] NFA0[6:0] NFA1[13:7] NFA1[6:0] ALCMIN[2:0] ALCLVL[3:0] ALCATK[3:0] NGTH[2:0] PLLN[3:0] 0 LIMDCY[3:0] HPFAPP JD_EN1[3:0] HPFCUT[2:0] ADCOSR 128 ADCLVOL[7:0] ADCRVOL[7:0] EQ1G[4:0] EQ2G[4:0] EQ3G[4:0] EQ4G[4:0] EQ5G[4:0] 10 0 LIMATK[3:0] LIMBOOST[3:0] 0 0 ROUT1EN OUT4EN BCP OUT4MIX EN LOUT1EN OUT3EN LRP 0 MCLKDIV[2:0] DCLKDIV[3:0] GPIO1GPU GPIO1GPD 0 0 JD_EN SOFT MUTE 0 OPCLKDIV JD_SEL 0 GPIO1POL 0 DACOSR 128 0 AMUTE OUT3MIX EN SLEEP PLLEN BOOST ENR WL WL8 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF'T VAL (HEX) Software reset MICBEN BOOST ENL 0 FMT DAC_COMP[1:0] BCLKDIV[2:0] SR[2:0] BIASEN INPGA ENR RMIXEN BUFIOEN INPPGA ENL LMIXEN VMIDSEL[1:0] ADCENR DACENR ADCENL DACENL MONO LOOP BACK MS SLOWCLK EN GPIO1SEL[2:0] 0 0 DACRPOL DACLPOL
0 1 2 3 4 5 6 7 8 9
00 01 02 03 04 05 06 07 08 09
000 000 000 050 000 140 080 000 000 000 0FF 0FF
ROUT2EN LOUT2EN
DLRSWAP ALRSWAP ADC_COMP[1:0] 0
10 0A 11 0B 12 0C 13 14 0E 15 0F 16 10 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 27 1B 28 1C 29 1D 30 1E 32 20 33 21 34 22 35 23 36 24 37 25 38 26 39 27 41 29 42 2A 43 2B
DACLVOL[7:0] DACRVOL[7:0] JD_EN0[3:0] 0 ADCRPOL ADCLPOL
0D Jack Detect Control
000 100 0FF 0FF 12C 02C 02C 02C 02C 008 032 000 000 000 000 000 038 00B 032 000 008 00C 093 0E9 000 000 000
w
PP, Rev 3.5, January 2007 89
WM8985
ADDR B[15:9] DEC HEX REGISTER NAME Input ctrl Left INP PGA gain ctrl Right INP PGA gain ctrl Left ADC Boost ctrl Right ADC Boost ctrl Output ctrl Left mixer ctrl Right mixer ctrl LOUT1 (HP) volume ctrl ROUT1 (HP) volume ctrl LOUT2 (SPK) volume ctrl ROUT2 (SPK) volume ctrl OUT3 mixer ctrl OUT4 (MONO) mixer ctrl Bias Control B8 B7 B6 B5 B4 B3 B2 B1
Pre-Production
B0 DEF'T VAL (HEX) MBVSEL INPGAVU INPGAVU PGA BOOSTL PGA BOOSTR 0 0 INPPGA ZCL INPPGA ZCR 0 0 0 AUXLMIXVOL[2:0] AUXRMIXVOL[2:0] OUT1VU OUT1VU OUT2VU OUT2VU 0 0 BIASCUT LOUT1ZC ROUT1ZC LOUT2ZC ROUT2ZC 0 OUT 3_2OUT4 0 LOUT1 MUTE ROUT1 MUTE LOUT2 MUTE ROUT2 MUTE OUT3 MUTE OUT4 MUTE 0 0 OUT4 ATTN 0 0 LMIX2 OUT4 00 R2_2 INPPGA INPPGA MUTEL INPPGA MUTER L2_2BOOSTVOL[2:0] R2_2BOOSTVOL[2:0] DACL2 RMIX DACR2 LMIX AUXL2 LMIX AUXR2 RMIX 0 RIN2 INPPGA RIP2 INPPGA 0 L2_2 INPPGA LIN2 INPPGA LIP2 INPPGA
44 2C 45 2D 46 2E 47 2F 48 30 49 31 50 32 51 33 52 34 53 35 54 36 55 37 56 38 57 39 61 3D
003 010 010 100 100 002 001 001 039 039 039 039
INPPGAVOLL[5:0] INPPGAVOLR[5:0] 0 0 0 BYPLMIXVOL[2:0] BYPRMIXVOL[2:0] LOUT1VOL[5:0] ROUT1VOL[5:0] LOUT2VOL[5:0] ROUT2VOL[5:0] OUT4_ 2OUT3 LDAC2 OUT4 BYPL2 OUT3 BYPR2 OUT4 00 LMIX2 OUT3 RMIX2 OUT4 LDAC2 OUT3 RDAC2 OUT4 0 AUXL2BOOSTVOL[2:0] AUXR2BOOSTVOL[2:0] TSOP CTRL TSDEN BYPL2 LMIX BYPR2 RMIX VROI DACL2 LMIX DACR2 RMIX
001 001 000
Table 53 WM8985 Register Map
w
PP, Rev 3.5, March 2007 90
Pre-Production
WM8985
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO
0 (00h) 1 (01h)
[8:0] 8 7
RESET
N/A 0
Software reset Reserved. Initialise to 0 OUT4 mixer enable 0=disabled 1=enabled OUT3 mixer enable 0=disabled 1=enabled PLL enable 0=PLL off 1=PLL on Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Analogue amplifier bias control 0=disabled 1=enabled Unused input/output tie off buffer enable 0=disabled 1=enabled Reference string impedance to VMID pin 00 = off (250k VMID to AGND1) 01=75k 10=300k 11=5k ROUT1 output enable 0=disabled 1=enabled LOUT1 output enable 0=disabled 1=enabled 0 = normal device operation 1 = residual current reduced in device standby mode Right channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Left channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Right channel input PGA enable 0 = disabled 1 = enabled Left channel input PGA enable 0 = disabled 1 = enabled
Resetting the Chip Power Management Power Management Master Clock and Phase Locked Loop (PLL) Input Signal Path Power Management Power Management Power Management
OUT4MIXEN
0
6
OUT3MIXEN
0
5
PLLEN
0
4
MICBEN
0
3
BIASEN
0
2
BUFIOEN
0
1:0
VMIDSEL[1:0]
00
2 (02h)
8
ROUT1EN
0
Power Management Power Management Power Management Power Management Power Management Power Management Power Management
7
LOUT1EN
0
6
SLEEP
0
5
BOOSTENR
0
4
BOOSTENL
0
3
INPPGAENR
0
2
INPPGAENL
0
w
PP, Rev 3.5, January 2007 91
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
1
ADCENR
0
Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled OUT4 enable 0 = disabled 1 = enabled OUT3 enable 0 = disabled 1 = enabled ROUT2 enable 0 = disabled 1 = enabled LOUT2 enable 0 = disabled 1 = enabled Reserved. Initialise to 0 Right output channel mixer enable: 0 = disabled 1 = enabled Left output channel mixer enable: 0 = disabled 1 = enabled Right channel DAC enable 0 = DAC disabled 1 = DAC enabled Left channel DAC enable 0 = DAC disabled 1 = DAC enabled BCLK polarity 0=normal 1=inverted LRC clock polarity 0=normal 1=inverted Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management Power Management Power Management Power Management
0
ADCENL
0
3 (03h)
8
OUT4EN
0
7
OUT3EN
0
6
ROUT2EN
0
5
LOUT2EN
0
4 3 RMIXEN
0 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs Digital Audio Interfaces Digital Audio Interfaces Digital Audio Interfaces
2
LMIXEN
0
1
DACENR
0
0
DACENL
0
4 (04h)
8
BCP
0
7
LRP
0
6:5
WL
10
4:3
FMT
10
Digital Audio Interfaces
w
PP, Rev 3.5, March 2007 92
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
2
DLRSWAP
0
Controls whether DAC data appears in `right' or `left' phases of LRC clock: 0=DAC data appear in `left' phase of LRC 1=DAC data appears in `right' phase of LRC Controls whether ADC data appears in `right' or `left' phases of LRC clock: 0=ADC data appear in `left' phase of LRC 1=ADC data appears in `right' phase of LRC Selects between stereo and mono device operation: 0=Stereo device operation 1=Mono device operation. Data appears in `left' phase of LRC Reserved. Initialise to 0 Companding Control 8-bit mode 0=off 1=device operates in 8-bit mode DAC companding 00=off (linear mode) 01=reserved 10=-law 11=A-law ADC companding 00=off (linear mode) 01=reserved 10=-law 11=A-law Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12
Digital Audio Interfaces
1
ALRSWAP
0
Digital Audio Interfaces
0
MONO
0
Digital Audio Interfaces
5 (05h)
8:6 5 WL8
000 0
Digital Audio Interfaces Digital Audio Interfaces
4:3
DAC_COMP
00
2:1
ADC_COMP
00
Digital Audio Interfaces
0
LOOPBACK
0
Digital Audio Interfaces
6 (06h)
8
CLKSEL
1
Digital Audio Interfaces
7:5
MCLKDIV
010
Digital Audio Interfaces
w
PP, Rev 3.5, January 2007 93
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
4:2
BCLKDIV
000
Configures the BCLK output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Reserved. Initialise to 0 Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8985 (MASTER) 0 = low power mode enabled 1 = low power mode disabled Controls clock division from SYSCLK to generate suitable class D clock. Recommended class D clock frequency = 1.4MHz. 0000 = divide by 1 0010 = divide by 2 0011 = divide by 3 0100 = divide by 4 0101 = divide by 5.5 0110 = divide by 6 1000 = divide by 8 1001 = divide by 12 1010 = divide by 16 Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled GPIO1 Open drain enable 0 = Open drain disabled 1 = Open drain enabled GPIO1 Internal pull-up enable: 0 = Internal pull-up disabled 1 = Internal pull-up enabled GPIO1 Internal pull-down enable: 0 = Internal pull-down disabled 1 = Internal pull-down enabled
Digital Audio Interfaces
1 0 MS
0 0
Digital Audio Interfaces
7 (07h)
8 7:4
M128ENB DCLKDIV
0 1000
Additional Control Class A / D Headphone Outputs
3:1
SR
000
Audio Sample Rates
0
SLOWCLKEN
0
Analogue Outputs
8 (08h)
8
GPIO1GP
0
General Purpose Input/Output (GPIO) General Purpose Input/Output (GPIO) General Purpose Input/Output (GPIO) PP, Rev 3.5, March 2007 94
7
GPIO1GPU
0
6
GPIO1GPD
0
w
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
5:4
OPCLKDIV
00
PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 GPIO1 Polarity invert 0=Non inverted 1=Inverted CSB/GPIO1 pin function select: 000= input (CSB/jack detection: depending on MODE setting) 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 1 111=logic 0 Reserved. Initialise to 00 Jack Detection Enable 0=disabled 1=enabled Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved Reserved. Initialise to 0 Reserved. Initialise to 0 Softmute enable: 0=Disabled 1=Enabled Reserved. Initialise to 0 DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Automute enable 0 = Amute disabled 1 = Amute enabled Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12)
General Purpose Input/Output (GPIO)
3
GPIO1POL
0
General Purpose Input/Output (GPIO) General Purpose Input/Output (GPIO)
2:0
GPIO1SEL [2:0]
000
9 (09h)
8:7 6 JD_EN
00 0
Output Switching (Jack Detect) Output Switching (Jack Detect)
5:4
JD_SEL
00
3:0 10 (0Ah) 8:7 6 SOFTMUTE
0 00 0
Output Signal Path
5:4 3 DACOSR128
00 0
Power Management Output Signal Path Output Signal Path Output Signal Path Digital to Analogue Converter (DAC)
2
AMUTE
0
1
DACPOLR
0
0
DACPOLL
0
11 (0Bh)
8
DACVU
N/A
w
PP, Rev 3.5, January 2007 95
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
7:0
DACVOLL
11111111
Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved. Initialise to 0 Output enabled when selected jack detection input is logic 1 [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 Output enabled when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode st 0=Audio mode (1 order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Figure 15 for details.
Digital to Analogue Converter (DAC)
12 (0Ch)
8 7:0
DACVU DACVOLR
N/A 11111111
Output Signal Path Output Signal Path
13 (0Dh)
8 7:4 JD_EN1
0 0000
Output Switching (Jack Detect)
3:0
JD_EN0
0000
Output Switching (Jack Detect)
14 (0Eh)
8
HPFEN
1
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management
7
HPFAPP
0
6:4
HPFCUT
000
3
ADCOSR 128
0
ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Reserved. Initialise to 0 ADC right channel polarity adjust: 0=normal 1=inverted ADC left channel polarity adjust: 0=normal 1=inverted ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 16 or 17)
2 1 ADCRPOL
0 0
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
0
ADCLPOL
0
15 (0Fh)
8
ADCVU
N/A
w
PP, Rev 3.5, March 2007 96
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
7:0
ADCVOLL
11111111
Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 16 or 17)
Analogue to Digital Converter (ADC)
16 (10h)
8
ADCVU
N/A
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
7:0
ADCVOLR
11111111
Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB 0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path Reserved. Initialise to 0 EQ Band 1 Cut-off Frequency: 00=80Hz 01=105Hz 10=135Hz 11=175Hz
18 (12h)
8
EQ3DMODE
1
Output Signal Path
7 6:5 EQ1C
0 01
Output Signal Path
4:0 19 (13h) 8
EQ1G EQ2BW
01100 0
EQ Band 1 Gain Control. See Table 31 for details. EQ Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved. Initialise to 0 EQ Band 2 Centre Frequency: 00=230Hz 01=300Hz 10=385Hz 11=500Hz
Output Signal Path Output Signal Path
7 6:5 EQ2C
0 01
Output Signal Path
4:0 20 (14h) 8
EQ2G EQ3BW
01100 0
EQ Band 2 Gain Control. See Table 31 for details. EQ Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved. Initialise to 0 EQ Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz
Output Signal Path Output Signal Path
7 6:5 EQ3C
0 01
Output Signal Path
4:0 21 (15h) 8
EQ3G EQ4BW
01100 0
EQ Band 3 Gain Control. See Table 31 for details. EQ Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved. Initialise to 0
Output Signal Path Output Signal Path
7
0
w
PP, Rev 3.5, January 2007 97
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
6:5
EQ4C
01
EQ Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz
Output Signal Path
4:0 22 (16h) 8:7 6:5
EQ4G
01100 0
EQ Band 4 Gain Control. See Table 31 for details. Reserved. Initialise to 0 EQ Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz
Output Signal Path Output Signal Path Output Signal Path
EQ5C
01
4:0 23 (17h) 8
EQ5G CLASSDEN
01100 0
EQ Band 5 Gain Control. See Table 31 for details. Enable signal for class D mode on LOUT2 and ROUT2 0 = Class AB mode 1 = Class D mode Reserved. Enable the DAC digital limiter: 0=disabled 1=enabled DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms
Output Signal Path Class D Control
7:0 24 (18h) 8 LIMEN
000 1000 0
Output Signal Path Output Signal Path
7:4
LIMDCY
0011
3:0
LIMATK
0010
Output Signal Path
w
PP, Rev 3.5, March 2007 98
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
25 (19h)
8:7 6:4 LIMLVL
00 000
Reserved. Initialise to 0 Programmable signal threshold level (determines level at which the DAC limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Output Signal Path
3:0
LIMBOOST
0000
DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch filter enable: 0=Disabled 1=Enabled Notch Filter a0 coefficient, bits [13:7]
Output Signal Path
27 (1Bh)
8
NFU
0
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
7
NFEN
0
6:0
NFA0[13:7]
0000000
28 (1Ch)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved. Initialise to 0 Notch Filter a0 coefficient, bits [6:0]
7 6:0 NFA0[6:0]
0 0000000
29 (1Dh)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved. Initialise to 0 Notch Filter a1 coefficient, bits [13:7]
7 6:0 NFA1[13:7]
0 0000000
30 (1Eh)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved. Initialise to 0 Notch Filter a1 coefficient, bits [6:0]
7 6:0 NFA1[6:0]
0 0000000
w
PP, Rev 3.5, January 2007 99
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
32 (20h)
8:7
ALCSEL
00
ALC function select: 00=ALC off 01=ALC right only 10=ALC left only 11=ALC both on Reserved. Initialise to 0 Set Maximum Gain of PGA 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB Set minimum gain of PGA 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC target - sets signal level at ADC input 1111 : -1.5dBFS 1110 : -1.5dBFS 1101 : -3dBFS 1100 : -4.5dBFS ...... (-1.5dB steps) 0001 : -21dBFS 0000 : -22.5dBFS
Input Limiter/ Automatic Level Control (ALC)
6 5:3 ALCMAXGAIN
0 111
Input Limiter/ Automatic Level Control (ALC)
2:0
ALCMINGAIN
000
Input Limiter/ Automatic Level Control (ALC)
33 (21h)
7:4
ALCHLD
0000
Input Limiter/ Automatic Level Control (ALC)
3:0
ALCLVL
1011
Input Limiter/ Automatic Level Control (ALC)
34 (22h)
8
ALCMODE
0
Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 1010 or higher 410us 820us 1.64ms 420ms Per 6dB 3.3ms 6.6ms 13.1ms 3.36s 90% of range 24ms 48ms 192ms 24.576s
Input Limiter/ Automatic Level Control (ALC) Input Limiter/ Automatic Level Control (ALC)
7:4
ALCDCY [3:0]
0011
... (time doubles with every step)
0011
Decay (gain ramp-up) time (ALCMODE ==1) PP, Rev 3.5, March 2007 100
w
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
Per step 0000 0001 0010 1010 3:0 ALCATK 0010 90.8us 181.6us 363.2us 93ms
Per 6dB 726.4us 1.453ms 2.905ms 744ms
90% of range 5.26ms 10.53ms 21.06ms 5.39s Input Limiter/ Automatic Level Control (ALC)
... (time doubles with every step) ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 1010 or higher 0010 104us 208us 416us 106ms Per 6dB 832us 1.664ms 3.328ms 852ms 90% of range 6ms 12ms 24.1ms 6.18s
... (time doubles with every step)
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363.2us 726.4us 186ms 90% of range 1.31ms 2.62ms 5.26ms 1.348s Input Limiter/ Automatic Level Control (ALC) Input Limiter/ Automatic Level Control (ALC)
... (time doubles with every step) 35 (23h) 8:4 3 NGEN 00000 0 Reserved. Initialise to 0 ALC Noise gate function enable 1 = enable 0 = disable ALC Noise gate threshold: 000=-39dB 001=-45dB 010=-51db ... (6dB steps) 111=-81dB Reserved. Initialise to 0 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input to PLL Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL)
2:0
NGTH
000
36 (24h)
8:5 4 PLLPRESCALE
0000 0
3:0
PLLN[3:0]
1000
Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Reserved. Initialise to 0 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
37 (25h)
8:6 5:0 PLLK[23:18]
000 01100
38 (26h)
8:0
PLLK[17:9]
010010011
w
PP, Rev 3.5, January 2007 101
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
39 (27h)
8:0
PLLK[8:0]
011101001
Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Reserved. Initialise to 0 Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect) Controls the OUT4 to ADC input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain OUT4 to L or R ADC input 0 = Right ADC input 1 = Left ADC input Reserved. Initialise to 0 VMID independent current bias control 0 = Disable VMID independent current bias 1 = Enable VMID independent current bias Left bypass path (from the Left channel input PGA stage) to right output mixer 0 = not selected 1 = selected Right bypass path (from the right channel input PGA stage) to Left output mixer 0 = not selected 1 = selected Reserved. Initialise to 0 Mute input to INVROUT2 mixer Mute input to INVROUT2 mixer AUXR input to ROUT2 inverter gain 000 = -15dB ... 111 = +6dB 0 = mute AUXR beep input 1 = enable AUXR beep input Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Reserved. Initialise to 0 Connect R2 pin to right channel input PGA positive terminal. 0=R2 not connected to input PGA 1=R2 connected to input PGA amplifier positive terminal (constant input impedance).
Master Clock and Phase Locked Loop (PLL) 3D Stereo Enhancement
41 (29h)
8:4 3:0 DEPTH3D
00000 0000
42 (2Ah)
8:6
OUT4_2ADCVOL
000
Analogue Outputs
5
OUT4_2LNR
0
4:0 2 POBCTRL
0 0000 0
43 (2Bh)
8
BYPL2RMIX
0
Analogue Outputs
7
BYPR2LMIX
0
Analogue Outputs
6 5 4 3:1 MUTERPGA2INV INVROUT2 BEEPVOL
0 0 0 000
Analogue Outputs Analogue Outputs Analogue Outputs
0 44 (2Ch) 8
BEEPEN MBVSEL
0 0
Analogue Outputs Input Signal Path
7 6 R2_2INPPGA
0 0
Input Signal Path
w
PP, Rev 3.5, March 2007 102
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
5
RIN2INPPGA
1
Connect RIN pin to right channel input PGA negative terminal. 0=RIN not connected to input PGA 1=RIN connected to right channel input PGA amplifier negative terminal. Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) Reserved. Initialise to 0 Connect L2 pin to left channel input PGA positive terminal. 0=L2 not connected to input PGA 1=L2 connected to input PGA amplifier positive terminal (constant input impedance). Connect LIN pin to left channel input PGA negative terminal. 0=LIN not connected to input PGA 1=LIN connected to input PGA amplifier negative terminal. Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Left channel input PGA zero cross enable: 0=Update gain when gain register changes st 1=Update gain on 1 zero cross after gain register write. Mute control for left channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Right channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Mute control for right channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage).
Input Signal Path
4
RIP2INPPGA
1
Input Signal Path
3 2 L2_2INPPGA
0 0
Input Signal Path
1
LIN2INPPGA
1
Input Signal Path
0
LIP2INPPGA
1
Input Signal Path
45 (2Dh)
8
INPPGAU
N/A
Input Signal Path Input Signal Path
7
INPPGAZCL
0
6
INPPGAMUTEL
0
Input Signal Path
5:0
INPPGAVOLL
010000
Input Signal Path
46 (2Eh)
8
INPPGAU
N/A
Input Signal Path Input Signal Path
7
INPPGAZCR
0
6
INPPGAMUTER
0
Input Signal Path
w
PP, Rev 3.5, January 2007 103
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
5:0
INPPGAVOLR
010000
Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Reserved. Initialise to 0 Controls the L2 pin to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved. Initialise to 0 Controls the auxilliary amplifer to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Reserved. Initialise to 0 Controls the R2 pin to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved. Initialise to 0 Controls the auxilliary amplifer to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved. Initialise to 0 Left DAC output to right output mixer 0 = not selected 1 = selected
Input Signal Path
47 (2Fh)
8
PGABOOSTL
1
Input Signal Path
7 6:4 L2_2BOOSTVOL
0 000
Input Signal Path
3 2:0 AUXL2BOOSTVOL
0 000
Input Signal Path
48 (30h)
8
PGABOOSTR
1
Input Signal Path
7 6:4 R2_2BOOSTVOL
0 000
Input Signal Path
3 2:0 AUXR2BOOSTVOL
0 000
Input Signal Path
49 (31h)
8:7 6 DACL2RMIX
00 0
Analogue Outputs
w
PP, Rev 3.5, March 2007 104
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
5
DACR2LMIX
0
Right DAC output to left output mixer 0 = not selected 1 = selected Reserved. Initialise to 0 Thermal Shutdown Output enable 0 = Disabled 1 = Enabled, i.e. all outputs will be disabled if TI set and the device junction temperature is more than 125C. Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Left Auxilliary input to left channel output mixer: 0 = not selected 1 = selected Left bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Left bypass path (from the left channel input boost output) to left output mixer 0 = not selected 1 = selected Left DAC output to left output mixer 0 = not selected 1 = selected Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Right Auxilliary input to right channel output mixer: 0 = not selected 1 = selected
Analogue Outputs
4:3 2 TSOPCTRL
00 0
Analogue Outputs
1
TSDEN
1
Analogue Outputs Analogue Outputs
0
VROI
0
50 (32h)
8:6
AUXLMIXVOL
000
Analogue Outputs
5
AUXL2LMIX
0
Analogue Outputs Analogue Outputs
4:2
BYPLMIXVOL
000
1
BYPL2L MIX
0
Analogue Outputs
0
DACL2L MIX AUXRMIXVOL
1
Analogue Outputs Analogue Outputs
51 (33h)
8:6
000
5
AUXR2RMIX
0
Analogue Outputs
w
PP, Rev 3.5, January 2007 105
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
4:2
BYPRMIXVOL
000
Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Right bypass path (from the right channel input boost output) to right output mixer 0 = not selected 1 = selected Right DAC output to right output mixer 0 = not selected 1 = selected LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53) Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left headphone output mute: 0 = Normal operation 1 = Mute Left headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53) Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Right headphone output mute: 0 = Normal operation 1 = Mute Right headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55) Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left speaker output mute: 0 = Normal operation 1 = Mute
Analogue Outputs
1
BYPR2RMIX
0
Analogue Outputs
0
DACR2RMIX
1
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
52 (34h)
8 7
OUT1VU LOUT1ZC
N/A 0
6
LOUT1MUTE
0
5:0
LOUT1VOL
111001
53 (35h)
8 7
OUT1VU ROUT1ZC
N/A 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
6
ROUT1MUTE
0
5:0
ROUT1VOL
111001
54 (36h)
8 7
OUT2VU LOUT2ZC
N/A 0
Analogue Outputs Analogue Outputs Analogue Outputs
6
LOUT2MUTE
0
w
PP, Rev 3.5, March 2007 106
Pre-Production
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
WM8985
REFER TO
5:0
LOUT2VOL
111001
Left speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55) Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Right speaker output mute: 0 = Normal operation 1 = Mute Right speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Reserved 0 = Output stage outputs OUT3 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID buffer in this mode. Reserved. Initialise to 0 OUT4 mixer output to OUT3 0 = disabled 1= enabled Left ADC input to OUT3 0 = disabled 1= enabled Left DAC mixer to OUT3 0 = disabled 1= enabled Left DAC output to OUT3 0 = disabled 1= enabled Reserved. Initialise to 0 OUT3 mixer output to OUT4 0 = disabled 1 = enabled 0 = Output stage outputs OUT4 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID buffer in this mode. 0=OUT4 normal output 1=OUT4 attenuated by 6dB Left DAC mixer to OUT4 0 = disabled 1= enabled Left DAC to OUT4 0 = disabled 1= enabled
Analogue Outputs
55 (37h)
8 7
OUT2VU ROUT2ZC
N/A 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
6
ROUT2MUTE
0
5:0
ROUT2VOL
111001
56 (38h)
8:7 6 OUT3MUTE
00 0
Analogue Outputs
5:4 3 OUT4_2OUT3
00 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
2
BYPL2OUT3
0
1
LMIX2OUT3
0
0
LDAC2OUT3
1
57 (39h)
8 7 OUT3_2OUT4
0 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
6
OUT4MUTE
0
5 4
HALFSIG LMIX2OUT4
0 0
3
LDAC2OUT4
0
w
PP, Rev 3.5, January 2007 107
WM8985
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
Pre-Production
REFER TO
2
BYPR2OUT4
0
Right ADC input to OUT4 0 = disabled 1= enabled Right DAC mixer to OUT4 0 = disabled 1= enabled Right DAC output to OUT4 0 = disabled 1= enabled Global bias control 0 = normal 1 = 0.5x Reserved. Initialise to 0
Analogue Outputs Analogue Outputs Analogue Outputs Bias Control
1
RMIX2OUT4
0
0
RDAC2OUT4
1
61 (39h)
8
0
7:0
000 0000
w
PP, Rev 3.5, March 2007 108
Pre-Production
WM8985
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter TEST CONDITIONS MIN TYP MAX UNIT
Passband Passband Ripple Stopband Stopband Attenuation Group Delay
ADC High Pass Filter
+/- 0.025dB -6dB
0 0.5fs
0.454fs +/- 0.025 dB dB 21/fs
0.546fs f > 0.546fs -60
High Pass Filter Corner Frequency
-3dB -0.5dB -0.1dB
3.7 10.4 21.6 0 0.5fs +/-0.035 0.546fs 0.454fs
Hz
DAC Filter
Passband Passband Ripple Stopband Stopband Attenuation Group Delay
Table 54 Digital Filter Characteristics
+/- 0.035dB -6dB
dB dB
f > 0.546fs
-55 29/fs
TERMINOLOGY
1. 2. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region
w
PP, Rev 3.5, January 2007 109
WM8985
DAC FILTER RESPONSES
20 0 -20
Response (dB) 3.05 3 2.95 2.9 2.85 2.8 2.75 2.7 2.65 2.6
Pre-Production
Response (dB)
-40 -60 -80 -100 -120 -140 -160 0 0.5 1 1.5 Frequency (fs) 2 2.5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (fs)
Figure 40 DAC Digital Filter Frequency Response (128xOSR)
20 0 -20
Figure 41 DAC Digital Filter Ripple (128xOSR)
3.05 3 2.95 2.9 2.85 2.8 2.75 2.7 2.65 2.6
Response (dB)
-60 -80 -100 -120 -140 -160 0 0.5 1 1.5 Frequency (fs) 2 2.5
Response (dB)
-40
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (fs)
Figure 42 DAC Digital Filter Frequency Response (64xOSR)
Figure 43 DAC Digital Filter Ripple (64xOSR)
ADC FILTER RESPONSES
0.2
0 -20 Response (dB)
0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 -0.2
0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-40 -60 -80 -100 -120
0
0.1
0.2 Frequency (Fs)
0.3
0.4
0.5
Figure 44 ADC Digital Filter Frequency Response
Figure 45 ADC Digital Filter Ripple
w
PP, Rev 3.5, March 2007 110
Pre-Production
WM8985
The WM8985 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off frequency.
HIGHPASS FILTER
5 0 -5 -10 Response (dB) -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 45 Frequency (Hz)
Figure 46 ADC Highpass Filter Response, HPFAPP=0
10 0 -10 Response (dB) -20 -30 -40
Response (dB)
10 0 -10 -20 -30 -40 -50 -60
-50 -60 0 200 400 600 Frequency (Hz) 800 1000 1200
-70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 47 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cut-off settings shown
Figure 48 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cut-off settings shown
10 0 -10 -20 Response (dB) -30 -40 -50 -60 -70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 49 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cut-off settings shown
w
PP, Rev 3.5, January 2007 111
WM8985
5-BAND EQUALISER
Pre-Production
The WM8985 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 50 to Figure 63 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter.
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
10
0
0
0
-5
-5
-10
-10
-15 -1 10
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 50 EQ Band 1 Low Frequency Shelf Filter Cut-offs
Figure 51 EQ Band 1 Gains for Lowest Cut-off Frequency
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
0 1 2 3 4 5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 52 EQ Band 2 - Peak Filter Centre Frequencies, EQ2BW=0
15
Figure 53
EQ Band 2 - Peak Filter Gains for Lowest Cut-off Frequency, EQ2BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 54 EQ Band 2 - EQ2BW=0, EQ2BW=1
w
PP, Rev 3.5, March 2007 112
Pre-Production
WM8985
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 55 EQ Band 3 - Peak Filter Centre Frequencies, EQ3BFigure 56
EQ Band 3 - Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0
15
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 57 EQ Band 3 - EQ3BW=0, EQ3BW=1
w
PP, Rev 3.5, January 2007 113
WM8985
Pre-Production
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 58 EQ Band 4 - Peak Filter Centre Frequencies, EQ3BW=0
15
Figure 59 EQ Band 4 - Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 60 EQ Band 4 - EQ3BW=0, EQ3BW=1
15 15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 61 EQ Band 5 High Frequency Shelf Filter Cut-offs
Figure 62 EQ Band 5 Gains for Lowest Cut-off Frequency
w
PP, Rev 3.5, March 2007 114
Pre-Production
WM8985
Figure 63 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the peak filters.
20
15
10
Magnitude (dB)
5
0
-5
-10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 63 Cumulative Frequency Boost/Cut
w
PP, Rev 3.5, January 2007 115
WM8985 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Pre-Production
Figure 64 External Component Diagram
1.
When operating LOUT2 and ROUT2 in class D mode, it is recommended that LC filtering is placed as close to the LOUT2 and ROUT2 pins as possible. Low ESR components should be used for maximum efficiency. It is recommended that a filter, consisting of a 33H inductor and a 220nF capacitor, is used for optimal performance. The addition of ferrite beads to the outputs of LOUT2 and ROUT2 will suppress any potential interference noise produced by the class D switching clocks.
2.
w
PP, Rev 3.5, March 2007 116
Pre-Production
WM8985
DM030.E
PACKAGE DIAGRAM
FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH
CORNER TIE BAR 5 25
D2 B D2/2 32
SEE DETAIL A
D
L 24 EXPOSED GROUND 6 PADDLE A 1 INDEX AREA (D/2 X E/2) E2/2
E2
SEE DETAIL B
E
17
8 2X 16 e 15 B 9 b 2X aaa C aaa C
BOTTOM VIEW
ccc C (A3) 1 A 0.08 C bbb M C A B 1
TOP VIEW
DETAIL A
32x b
CORNER TIE BAR 5
C
SIDE VIEW
SEATING PLANE
1 e/2 TERMINAL TIP
A1
L
43 0. m m 0.5
32x K
DETAIL B
DATUM
66 m m
EXPOSED GROUND PADDLE
R
1 L1
e
Symbols A A1 A3 b D D2 E E2 e L L1 R K aaa bbb ccc REF: MIN 0.85 0 0.18 4.90 3.2 4.90 3.2 0.35
1 b(min)/2 0.20 Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-2
Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 5.10 3.3 3.4 5.00 5.10 3.3 3.4 0.5 BSC 0.4 0.45 0.1
L1
R
NOTE
1 2 2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
w
PP, Rev 3.5, January 2007 117
WM8985
Pre-Production
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
w
PP, Rev 3.5, March 2007 118

▲Up To Search▲

Price & Availability of WM898507

	To Download WM898507 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .